This board doesn't use trapped I/O for anything, so just kill off the
select. This was causing problems in the unhandled page fault die path.
Signed-off-by: NPaul Mundt <lethal@linux-sh.org>

This builds on top of the previous reversion and implements a special
on_each_cpu() variant that simple disables preemption across the call
while leaving the interrupt state to the function itself. There were some
unintended consequences with IRQ disabling in some of these paths on UP
that ran in to a deadlock scenario with IRQs being missed.
Signed-off-by: NPaul Mundt <lethal@linux-sh.org>

This reverts commit 64a6d722.

Unfortunately we can't use on_each_cpu() for all of the cache ops, as
some of them only require preempt disabling. This seems to be the same
issue that impacts the mips r4k caches, where this code was based on.
This fixes up a deadlock that showed up in some IRQ context cases.
Signed-off-by: NPaul Mundt <lethal@linux-sh.org>

The kgdb stub has traditionally tied in to the NMI slot, and manually
handled debounce. Now that we have a generic way to do this instead, all
of the stub-specific debounce silliness can be killed off.
Signed-off-by: NPaul Mundt <lethal@linux-sh.org>

This implements support for NMI debugging that was shamelessly copied
from the avr32 port. A bit of special magic is needed in the interrupt
exception path given that the NMI exception handler is stubbed in to the
regular exception handling table despite being reported in INTEVT. So we
mangle the lookup and kick off an EXPEVT-style exception dispatch from
the INTEVT path for exceptions that do_IRQ() has no chance of handling.
As a result, we also drop the evt2irq() conversion from the do_IRQ() path
and just do it in assembly.
Signed-off-by: NPaul Mundt <lethal@linux-sh.org>

Conflicts:
	arch/sh/mm/cache-sh4.c

This adopts the special-cased 2-way write-through dcache flusher for
N-ways and moves it in to the generic path. Assignment is done at runtime
via the check for the CCR_CACHE_WT bit in the same path as the per-way
writeback flushers.
Signed-off-by: NMatt Fleming <matt@console-pimps.org>
Signed-off-by: NPaul Mundt <lethal@linux-sh.org>

This fixes up the simplified multi-evt handling when sparseirq support is
enabled. While vectors are redirected through the single unique masking
source, each one of the redirected vectors still requires its own backing
irq_desc, which needs to be manually allocated in the sparseirq case.
Signed-off-by: NPaul Mundt <lethal@linux-sh.org>

A couple of these popped up on the sh2a build, causing build failures.
Signed-off-by: NPaul Mundt <lethal@linux-sh.org>

Some unaligned accesses are completely expected. For example, the
trapped_io code uses the unaligned access fixup code path so there's no
need to warn about having to fixup the unaligned access.
Signed-off-by: NMatt Fleming <matt@console-pimps.org>
Signed-off-by: NPaul Mundt <lethal@linux-sh.org>

Fix up PCA9564 resources on 32bit MMU mode using prototype board.
Signed-off-by: NYoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
Tested-by: NRaul Porcel <armin76@gentoo.org>
Signed-off-by: NPaul Mundt <lethal@linux-sh.org>

Signed-off-by: NPaul Mundt <lethal@linux-sh.org>

Signed-off-by: NKuninori Morimoto <morimoto.kuninori@renesas.com>
Signed-off-by: NPaul Mundt <lethal@linux-sh.org>

Signed-off-by: NKuninori Morimoto <morimoto.kuninori@renesas.com>
Signed-off-by: NPaul Mundt <lethal@linux-sh.org>

Signed-off-by: NKuninori Morimoto <morimoto.kuninori@renesas.com>
Signed-off-by: NPaul Mundt <lethal@linux-sh.org>

Signed-off-by: NKuninori Morimoto <morimoto.kuninori@renesas.com>
Signed-off-by: NPaul Mundt <lethal@linux-sh.org>

Signed-off-by: NKuninori Morimoto <morimoto.kuninori@renesas.com>
Signed-off-by: NPaul Mundt <lethal@linux-sh.org>

Signed-off-by: NKuninori Morimoto <morimoto.kuninori@renesas.com>
Signed-off-by: NPaul Mundt <lethal@linux-sh.org>

Signed-off-by: NKuninori Morimoto <morimoto.kuninori@renesas.com>
Signed-off-by: NPaul Mundt <lethal@linux-sh.org>

Signed-off-by: NPaul Mundt <lethal@linux-sh.org>

This is supposed to be the equivalent of __NR_syscalls, not
__NR_syscalls -1. The x86 code this was based on had simply fallen
out of sync at the time this was implemented. Fix it up now.

As a result, tracing of __NR_perf_counter_open works as advertised.
Signed-off-by: NPaul Mundt <lethal@linux-sh.org>

Needed by ftrace changes in -tip.
Signed-off-by: NPaul Mundt <lethal@linux-sh.org>

In certain configurations linux/err.h is not included through alternate
means, resulting in:

drivers/usb/gadget/m66592-udc.c:1646: error: implicit declaration of function 'IS_ERR'
drivers/usb/gadget/m66592-udc.c:1649: error: implicit declaration of function 'PTR_ERR'
distcc[15083] ERROR: compile drivers/usb/gadget/m66592-udc.c on localhost failed
make[3]: *** [drivers/usb/gadget/m66592-udc.o] Error 1
make[2]: *** [drivers/usb/gadget] Error 2
make[1]: *** [drivers] Error 2
make: *** [sub-make] Error 2

Caught with an ARM config in -next.
Signed-off-by: NPaul Mundt <lethal@linux-sh.org>

This patch changes the way in which "multi-evt" interrups are handled.
The intc_evt2irq_table and related intc_evt2irq() have been removed and
the "redirecting" handler is installed for the coupled interrupts.

Thanks to that the do_IRQ() function don't have to use another level
of indirection for all the interrupts...
Signed-off-by: NPawel Moll <pawel.moll@st.com>
Signed-off-by: NStuart Menefy <stuart.menefy@st.com>
Signed-off-by: NPaul Mundt <lethal@linux-sh.org>

sys_cacheflush should return with EINVAL if the cache parameter is not
one of ICACHE, DCACHE or BCACHE.
So, we need to include 0 in the first check.

It also adds the three definitions above as wrapper of the existent macros.

PS: ltp cacheflush01 test now passes.
Signed-off-by: NGiuseppe Cavallaro <peppe.cavallaro@st.com>
Signed-off-by: NStuart Menefy <stuart.menefy@st.com>
Signed-off-by: NPaul Mundt <lethal@linux-sh.org>

Change the method used to flush the cache in write-through mode to
avoid corrupted data being written back to memory.
Signed-off-by: NStuart Menefy <stuart.menefy@st.com>
Signed-off-by: NPaul Mundt <lethal@linux-sh.org>

Allow peripherals before the start of RAM to be remapped.
Signed-off-by: NStuart Menefy <stuart.menefy@st.com>
Signed-off-by: NPaul Mundt <lethal@linux-sh.org>

It is possible for the CPU to re-enable it's interrupt block bit
before the write to the interrupt controller has actually masked out
the external interupt at the controller. We get around this by
reading back from the interrupt controller which will ensure the
write has happened.
Signed-off-by: NStuart Menefy <stuart.menefy@st.com>
Signed-off-by: NPaul Mundt <lethal@linux-sh.org>

Signed-off-by: NStuart Menefy <stuart.menefy@st.com>
Signed-off-by: NPaul Mundt <lethal@linux-sh.org>

Adds a system call to allow user code to flush code from the cache.
You can use instructions for the data side, but the iside can
only be done by a flush ROM which really only works with a direct
mapped cache. The later SH4's have 2 way Iside, so this call allows
a portable way to flush the cache.
Signed-off-by: NStuart Menefy <stuart.menefy@st.com>
Signed-off-by: NPaul Mundt <lethal@linux-sh.org>

This is a pure documentation, to try to explain why the cache flushing code
for the SH4 is implemented the way it is.
Signed-off-by: NStuart Menefy <stuart.menefy@st.com>
Signed-off-by: NPaul Mundt <lethal@linux-sh.org>

Optimise memcpy_to/fromio. This is used extensivly by MTD, so is a
worthwhile performance gain. The main savings come from not repeatedly
calling readl/writel, and doing word instead of byte at a time
transfers. Also using "movca.l" on SH4 gives a small performance win.
Signed-off-by: NStuart Menefy <stuart.menefy@st.com>
Signed-off-by: NPaul Mundt <lethal@linux-sh.org>

After performing the port2addr conversion, and checking that the data is
correctly aligned, simply call __raw_readsX/writesX. These have already been
optimised.
Signed-off-by: NStuart Menefy <stuart.menefy@st.com>
Signed-off-by: NPaul Mundt <lethal@linux-sh.org>

Reading from the ROM is not a good idea as it could disturb some
flash operation that it is in progress.
Signed-off-by: NStuart Menefy <stuart.menefy@st.com>
Signed-off-by: NPaul Mundt <lethal@linux-sh.org>

The SH instruction set has several instructions which accept an 8 bit
immediate operand. For logical instructions this operand is zero extended,
for arithmetic instructions the operand is sign extended. After adding an
option to the assembler to check this, it was found that several pieces
of assembly code were assuming this behaviour, and in one case
getting it wrong.

So this patch explicitly sign extends any immediate operands, which makes
it obvious what is happening, and fixes the one case which got it wrong.
Signed-off-by: NStuart Menefy <stuart.menefy@st.com>
Signed-off-by: NPaul Mundt <lethal@linux-sh.org>

So far kernel command line arguments could be passed in by a bootloader
or defined as CONFIG_CMDLINE, which completely overwriting the first one.

This change allows a developer to declare selected kernel parameters in
a kernel configuration (eg. project-specific defconfig), retaining
possibility of passing others by a bootloader.

The obvious examples of the first type are MTD partition or
bigphysarea-like region definitions, while "debug" option or network
configuration should be given by a bootloader or a JTAG boot script.
Signed-off-by: NPawel Moll <pawel.moll@st.com>
Signed-off-by: NStuart Menefy <stuart.menefy@st.com>
Signed-off-by: NPaul Mundt <lethal@linux-sh.org>

This patches will trigger a reboot using the watchdog
timer instead of double fault.  Unlike the previous
method, this one actually works in 32 bit mode.

Reset should also be cleaner.
Signed-off-by: NJon Frosdick <jon.frosdick@st.com>
Signed-off-by: NCarl Shaw <carl.shaw@st.com>
Signed-off-by: NPaul Mundt <lethal@linux-sh.org>

Save the VBR allowing GDB to dump full registers set but do not reload it
as soon as the kgdb_handle_exception is invoked.
Signed-off-by: NGiuseppe Cavallaro <peppe.cavallaro@st.com>
Signed-off-by: NStuart Menefy <stuart.menefy@st.com>
Signed-off-by: NPaul Mundt <lethal@linux-sh.org>

The synopsys PCI cell used in the later STMicro chips requires code to
be run in order to do IO cycles, rather than just memory mapping the IO
space. Rather than extending the existing SH infrastructure to allow
this, use the GENERIC_IOMAP implmentation to save re-inventing the
wheel.

This set of changes allows the SH to be built with GENERIC_IOMAP
enabled, it just ifdef's out the functions provided by the GENERIC_IOMAP
implementation, and provides a few required missing functions.
Signed-off-by: NDavid McKay <david.mckay@st.com>
Signed-off-by: NPaul Mundt <lethal@linux-sh.org>