This is not needed as irq_set_wake is
only used for suspend to ram which is not
a requirement for bringing up boards using DT.
Reported-by: NMagnus Damm <magnus.damm@gmail.com>
Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>

Z and ZG clocks on sh73a0 have pll0 as their parent, not pll1.
Signed-off-by: NGuennadi Liakhovetski <g.liakhovetski@gmx.de>
Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>

Adjust emev2_init_delay() and emev2_add_standard_devices_dt()
to become static. They are not used outside this file anyway.
Signed-off-by: NMagnus Damm <damm@opensource.se>
Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>

Update the SMP code for EMEV2 to make use of the
shared SCU function scu_power_mode() together with
the early setup code in shmobile_secondary_vector_scu.

With this patch in place the secondary CPUs modify the
SCU setting during early boot instead of letting other
CPUs deal with the coherency setting before boot. In
other words, we used to setup coherency before boot
in emev2_boot_secondary() but that bit is now instead
handled by the code in shmobile_secondary_vector_scu.
Signed-off-by: NMagnus Damm <damm@opensource.se>
Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>

Update the code in headsmp-scu.S to use a global
shmobile_scu_base variable both for convenient SCU
base address storage and for the early SCU setup
code in shmobile_secondary_vector_scu.

With this patch applied r8a7779, sh73a0 and EMEV2
all make use of the global shmobile_scu_base
variable. However only sh73a0 makes use of the SCU
bring up code in shmobile_secondary_vector_scu.
Signed-off-by: NMagnus Damm <damm@opensource.se>
Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>

Rename headsmp-sh73a0.S into headsmp-scu.S and
introduce shmobile_secondary_vector_scu().

The goal is to be able to share the function
above between all mach-shmobile SoCs that use
SCU for SMP. So far only sh73a0 use this.

At this time the SCU base address is still hard
coded in headsmp-scu.S to 0xf0000000, but this
will be changed in the future.
Signed-off-by: NMagnus Damm <damm@opensource.se>
Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>

Rename the static scu_base variable into shmobile_scu_base.

Later in the series the shmobile_scu_base variable will be
made into a global variable so this is preparation only.
Signed-off-by: NMagnus Damm <damm@opensource.se>
Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>

Replace scu_base_addr() with a static shmobile_scu_base
variable and introduce R8A7779_SCU_BASE.

Later in the series the shmobile_scu_base variable will be
made into a global variable so this is preparation only.
Signed-off-by: NMagnus Damm <damm@opensource.se>
Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>

Replace scu_base_addr() with a static shmobile_scu_base
variable and introduce SH73A0_SCU_BASE.

Later in the series the shmobile_scu_base variable will be
made into a global variable so this is preparation only.
Signed-off-by: NMagnus Damm <damm@opensource.se>
Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>

Allow a minimal setup of the r8a7779 SoC using a flattened device tree.
In particular, configure the i2c and ethernet controllers using a
flattened device tree.

SCI serial controller and TMU clock source, whose drivers do not yet
support configuration using a flattened device tree, are still configured
using C code in order to allow booting of a board with this SoC.

The ethernet controller also requires a regulator which is a board property.
A sample snippet DT for the marzen board is as follows:

/dts-v1/;
/include/ "r8a7779.dtsi"

/ {
	fixedregulator3v3: fixedregulator@0 {
		compatible = "regulator-fixed";
		regulator-name = "fixed-3.3V";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
		regulator-boot-on;
		regulator-always-on;
	};
};

&lan0 {
	vddvario-supply = <&fixedregulator3v3>;
	vdd33a-supply = <&fixedregulator3v3>;
};
Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>

This allows the GIC interrupt controller of the  r8a7779 SoC to be
initialised using a flattened device tree blob.
Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>

---

v3
* Fix copy-paste error and use unique reg values for each CPU

v2
As suggested by Mark Rutland
* Add reg and device_type to cpus
* Remove #address-cells from gic

Add clock lookup entries for SDHI and MMCIF device names, for the FDT case.
Signed-off-by: NGuennadi Liakhovetski <g.liakhovetski@gmx.de>
Acked-by: NLaurent Pinchart <laurent.pinchart@ideasonboard.com>
Acked-by: NLinus Walleij <linus.walleij@linaro.org>
[horms+renesas@verge.net.au: resolved trivial conflict in clock-r8a7740.c]
Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>

Reduce the number of lines of code in smp-emev2.c
by getting rid of the emev2_get_core_count() function.
Signed-off-by: NMagnus Damm <damm@opensource.se>
Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>

Reduce the number of lines of code in smp-r8a7779.c
by getting rid of the r8a7779_get_core_count() function.
Signed-off-by: NMagnus Damm <damm@opensource.se>
Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>

Reduce the number of lines of code in smp-sh73a0.c
by getting rid of the sh73a0_get_core_count() function.
Signed-off-by: NMagnus Damm <damm@opensource.se>
Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>

Move the boot vector setup code for the EMEV2 SoC to match
the sh73a0 and r8a7779 implementations. With this in place
all SoC specific SMP implementations for mach-shmobile uses
the ->smp_prepare_cpus() callback to setup the boot vector.
Signed-off-by: NMagnus Damm <damm@opensource.se>
Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>

Remove partial CPU hotplug support from EMEV2 SMP code.

The upstream EMEV2 SMP support code has no CPU shutdown or
reset ability so we cannot reboot the secondary CPU cores.

Regular SMP operation is however still working as expected.
Signed-off-by: NMagnus Damm <damm@opensource.se>
Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>

This file has no SoC-specific references in it, and
fortunately it is still independent of OF so there
is no real reason to drag in these headers.
Signed-off-by: NMagnus Damm <damm@opensource.se>
Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>

After discussion on the linux-sh mailing list and reference to the
hardware documentation it appears that 'TMU00', 'TMU01' and 'TMU02'
use a common clock.

The sh_tmu.1 portion of this change resolves a regression introduced in
58079fa7 (ARM: shmobile: r8a7779: Correct
TMU clock support) and fixes a regression introduced by that patch. That
patch is queued up for v3.9.

...
hub 4-0:1.0: USB hub found
hub 4-0:1.0: 2 ports detected
INFO: rcu_sched self-detected stall on CPUINFO: rcu_sched detected stalls on
+CPUs/tasks: { 1} (detected by 2, t=279640 jiffies, g=4294967052, c=4294967051,
+q=38)
Task dump for CPU 1:
swapper/0       R running      0     1      0 0x00000002
[<c02b8f5c>] (__schedule+0x1b0/0x4c0) from [<c013c590>] (__loop_delay+0x4/0xc)

 { 1}  (t=279640 jiffies g=4294967052 c=4294967052 q=37)
[<c000ef9c>] (unwind_backtrace+0x0/0xf8) from [<c0068488>]
+(rcu_check_callbacks+0x218/0x6b8)
[<c0068488>] (rcu_check_callbacks+0x218/0x6b8) from [<c0026774>]
+(update_process_times+0x38/0x4c)
[<c0026774>] (update_process_times+0x38/0x4c) from [<c00569e0>]
+(tick_nohz_handler+0xb4/0x11c)
[<c00569e0>] (tick_nohz_handler+0xb4/0x11c) from [<c000e518>]
+(twd_handler+0x34/0x44)
[<c000e518>] (twd_handler+0x34/0x44) from [<c0063484>]
+(handle_percpu_devid_irq+0x68/0x80)
[<c0063484>] (handle_percpu_devid_irq+0x68/0x80) from [<c005febc>]
+(generic_handle_irq+0x20/0x30)
[<c005febc>] (generic_handle_irq+0x20/0x30) from [<c000a5ec>]
+(handle_IRQ+0x40/0x90)
[<c000a5ec>] (handle_IRQ+0x40/0x90) from [<c000934c>] (gic_handle_irq+0x2c/0x5c)
[<c000934c>] (gic_handle_irq+0x2c/0x5c) from [<c0009a40>] (__irq_svc+0x40/0x50)
Exception stack(0xef03ddf8 to 0xef03de40)
dde0:                                                       000001c1 ffffffff
de00: 000001d8 01bf01bf ef35ec40 ef35e800 ef35ec6c 0000002b ef35ec68 c013c560
de20: c0392994 60000113 00000000 ef03de40 c01a5d40 c013c590 20000113 ffffffff
[<c0009a40>] (__irq_svc+0x40/0x50) from [<c013c590>] (__loop_delay+0x4/0xc)

Cc: Denis Oliver Kropp <dok@directfb.org>
Cc: Magnus Damm <damm@opensource.se>
Cc: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Cc: Paul Mundt <lethal@linux-sh.org>
Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>

mach-socfpga is another platform that needs to use
v7_invalidate_l1 to bringup additional cores. There was a comment that
the ideal place for v7_invalidate_l1 should be in arm/mm/cache-v7.S
Signed-off-by: NDinh Nguyen <dinguyen@altera.com>
Acked-by: NSimon Horman <horms+renesas@verge.net.au>
Acked-by: NStephen Warren <swarren@nvidia.com>
Reviewed-by: NPavel Machek <pavel@denx.de>
Reviewed-by: NSantosh Shilimkar <santosh.shilimkar@ti.com>
Tested-by: NPavel Machek <pavel@denx.de>
Tested-by: NStephen Warren <swarren@nvidia.com>
Cc: Arnd Bergmann <arnd@arndb.de>
Cc: Russell King <linux@arm.linux.org.uk>
Cc: Olof Johansson <olof@lixom.net>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Rob Herring <rob.herring@calxeda.com>
Cc: Sascha Hauer <kernel@pengutronix.de>
Cc: Magnus Damm <magnus.damm@gmail.com>
Signed-off-by: NOlof Johansson <olof@lixom.net>

This patch adds an IPMMU device and notifies the IPMMU driver which
devices are connected via the IPMMU module.  All devices connected to the main
memory bus via the IPMMU module MUST be registered when SHMOBILE_IPMMU and
SHMOBILE_IOMMU are enabled because physical address cannot be used
while the IPMMU module's MMU function is enabled.
Signed-off-by: NHideki EIRAKU <hdk@igel.co.jp>
Acked-by: NPaul Mundt <lethal@linux-sh.org>
Acked-by: NSimon Horman <horms+renesas@verge.net.au>
Signed-off-by: NJoerg Roedel <joro@8bytes.org>

This patch adds an IPMMU device and notifies the IPMMU driver which
devices are connected via the IPMMU module.  All devices connected to the main
memory bus via the IPMMU module MUST be registered when SHMOBILE_IPMMU and
SHMOBILE_IOMMU are enabled because physical address cannot be used
while the IPMMU module's MMU function is enabled.
Signed-off-by: NHideki EIRAKU <hdk@igel.co.jp>
Acked-by: NPaul Mundt <lethal@linux-sh.org>
Acked-by: NSimon Horman <horms+renesas@verge.net.au>
Signed-off-by: NJoerg Roedel <joro@8bytes.org>

This patch adds an IPMMU device and notifies the IPMMU driver which
devices are connected via the IPMMU module.  All devices connected to the main
memory bus via the IPMMU module MUST be registered when SHMOBILE_IPMMU and
SHMOBILE_IOMMU are enabled because physical address cannot be used
while the IPMMU module's MMU function is enabled.
Signed-off-by: NHideki EIRAKU <hdk@igel.co.jp>
Acked-by: NPaul Mundt <lethal@linux-sh.org>
Acked-by: NSimon Horman <horms+renesas@verge.net.au>
Signed-off-by: NJoerg Roedel <joro@8bytes.org>

Register ARM architected timer by default for all mach-shmobile
systems using late timer.
Signed-off-by: NMagnus Damm <damm@opensource.se>
Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>

During code review it was noticed that the clock value for
TMU01 was incorrect and the value for TMU02 was missing.

For reference: As of 3.8-rc6 there are no in-tree consumes of these clocks.
Reported-by: NDenis Oliver Kropp <dok@directfb.org>
Reviewed-by: NMagnus Damm <damm@opensource.se>
Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>

Previously clock rates were set after initialization of timer.
Therefore the timer used the default extal1 clock rate (25MHz)
instead of the correct rate for this board (24MHz).
Signed-off-by: NHideki EIRAKU <hdk@igel.co.jp>
Acked-by: NKuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>

sh73a0 deals fine with disabling any core, so we should permit it.
Signed-off-by: NUlrich Hecht <ulrich.hecht@gmail.com>
Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>

Method to disable any core to be used on platforms where CPU0 does not
need special treatment.
Signed-off-by: NUlrich Hecht <ulrich.hecht@gmail.com>
Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>

Replace occurences of gpio_request() and gpio_direction_*() by calls to
gpio_request_one().
Signed-off-by: NLaurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Acked-by: NGuennadi Liakhovetski <g.liakhovetski@gmx.de>
Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>

Replace occurences of gpio_request() and gpio_direction_*() by calls to
gpio_request_one().
Signed-off-by: NLaurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Acked-by: NGuennadi Liakhovetski <g.liakhovetski@gmx.de>
Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>

Replace occurences of gpio_request() and gpio_direction_*() by calls to
gpio_request_one().
Signed-off-by: NLaurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Acked-by: NGuennadi Liakhovetski <g.liakhovetski@gmx.de>
Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>

Replace occurences of gpio_request() and gpio_direction_*() by calls to
gpio_request_one().
Signed-off-by: NLaurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Acked-by: NGuennadi Liakhovetski <g.liakhovetski@gmx.de>
Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>

The GPIO is already configured as an output, there's no reason to use
gpio_direction_output() just to set the output value. Use
gpio_set_value() instead.
Signed-off-by: NLaurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Acked-by: NGuennadi Liakhovetski <g.liakhovetski@gmx.de>
Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>

Replace occurences of gpio_request() and gpio_direction_*() by calls to
gpio_request_one().
Signed-off-by: NLaurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Acked-by: NGuennadi Liakhovetski <g.liakhovetski@gmx.de>
Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>

Replace occurences of gpio_request() and gpio_direction_*() by calls to
gpio_request_one().
Signed-off-by: NLaurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Acked-by: NGuennadi Liakhovetski <g.liakhovetski@gmx.de>
Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>

Replace occurences of gpio_request() and gpio_direction_*() by calls to
gpio_request_one().
Signed-off-by: NLaurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Acked-by: NGuennadi Liakhovetski <g.liakhovetski@gmx.de>
Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>

This patch tidyup scif .irqs settings by using
SCIx_IRQ_MUXED() macro.
Signed-off-by: NKuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>

This device also requires a voltage regulator which
should be defined in a board-specific maner. An example
dts snipped follows.

/ {
	fixedregulator1v8: fixedregulator@0 {
		compatible = "regulator-fixed";
		regulator-name = "fixed-1.8V";
		regulator-min-microvolt = <1800000>;
		regulator-max-microvolt = <1800000>;
	};
};

&mmcif {
	vmmc-supply = <&fixedregulator1v8>;
	vqmmc-supply = <&fixedregulator1v8>;
};
Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>

Allow a minimal setup of the sh73a0 SoC using a flattened device tree.
In particular, Configure the i2c controllers using a flattened device tree.

SCI serial controller and CMT clock source, whose drivers do not yet
support configuration using a flattened device tree, are still configured
using C code in order to allow booting of a board with this SoC.

*** Please note that the clock initialisation scheme used in
    this patch does not currently work with SMP as there
    is a yet to be resolved lock-up in workqueue initialisation.

    CONFIG_SMP must be disabled when using this code. ***

Includes update from Thierry Reding to no longer use gic_handle_irq()

Cc: Thierry Reding <thierry.reding@avionic-design.de>
Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>

fix

This allows the GIC interrupt controller of the sh73a0 SoC to be
initialised using a flattened device tree blob.

It does not allow the INTC interrupt controller which is also present on
the sh73a0 SoC to be enabled via device tree.  Nor does it handle sharing
of interrupts between the GIC and INTC interrupt controllers.

This limits the usefulness of this code to applications which only wish to
access devices which use interrupts that can be handled by the GIC
interrupt controller. Other applications should, for now, continue using
non-device tree initialisation of the sh72a0 interrupt controllers.

Includes update to use irqchip_init() by Thierry Reding

Cc: Thierry Reding <thierry.reding@avionic-design.de>
Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>