Merge tag 'sunxi-clocks-for-3.18' of git://git.kernel.org/pub/scm/linux/kernel/git/mripard/linux into clk-next

Allwinner Clocks Additions for 3.18

The most important part of this serie is the addition of the phase API to
handle the MMC clocks in the Allwinner SoCs.

Apart from that, the A23 gained a new mbus driver, and there's a fix for a
incorrect divider table on the APB0 clock.

Merge tag 'v3.18-rockchip-cpuclk' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into clk-next

CPU clock handling for Rockchip SoCs

This adds the necessary soc-specific divider values and switches the armclk
to use the newly introduced cpuclk type.
Signed-off-by: NHeiko Stuebner <heiko@sntech.de>
Reviewed-by: NDoug Anderson <dianders@chromium.org>
Tested-by: NDoug Anderson <dianders@chromium.org>

When changing the armclk on Rockchip SoCs it is supposed to be reparented
to an alternate parent before changing the underlying pll and back after
the change. Additionally there exist clocks that are very tightly bound to
the armclk whose divider values are set according to the armclk rate.

Add a special clock-type to handle all that. The rate table and divider
values will be supplied from the soc-specific clock controllers.
Signed-off-by: NHeiko Stuebner <heiko@sntech.de>
Reviewed-by: NDoug Anderson <dianders@chromium.org>
On a rk3288-board:
Tested-by: NDoug Anderson <dianders@chromium.org>

Rockchip SoCs contain clocks tightly bound to the armclk, where the best
rate / divider is supplied by the vendor after careful measuring.
Often this ideal rate may be greater than the current rate.

Therefore prevent the ccf from trying to set these dividers itself by
setting them to read-only.

In the case of the rk3066, this also includes the aclk_cpu, which makes it
necessary to also split its direct child-clocks (pclk_cpu, hclk_cpu, ...)
into individual definitions for rk3066 and rk3188.
Signed-off-by: NHeiko Stuebner <heiko@sntech.de>
Reviewed-by: NDoug Anderson <dianders@chromium.org>
Tested-by: NDoug Anderson <dianders@chromium.org>

aclk_cpu_pre on the rk3188 can either be sourced from the armclk or the gpll.
To reduce complexity on apll changes caused by cpufreq, reparent it always
to the gpll source.

If really necessary it could be reparented back on a per board level using
the assigned-clocks mechanism.
Signed-off-by: NHeiko Stuebner <heiko@sntech.de>

In RK3288, APLL lock status bit is in GRF_SOC_STATUS1,
but in RK3188, is GRFSOC_STATUS0.
Signed-off-by: NJianqun <jay.xu@rock-chips.com>

Also name the constant accordingly as GRF_SOC_STATUS1
to prevent confusion.
Signed-off-by: NHeiko Stuebner <heiko@sntech.de>
Reviewed-by: NDoug Anderson <dianders@chromium.org>
Tested-by: NDoug Anderson <dianders@chromium.org>

The register providing the pll lock status is at a different address on the
rk3066. The error became apparent while working on cpufreq support for
the rockchip SoCs.
Signed-off-by: NHeiko Stuebner <heiko@sntech.de>

The Rockchip PLL code switches into slow mode (AKA bypass more AKA
24MHz mode) before actually changing the PLL.  This keeps anyone from
using the PLL while it's changing.  However, in all known Rockchip
SoCs nobody should ever see the 24MHz when changing the PLL supplying
the armclk because we should reparent children to an alternate
(faster than 24MHz) PLL.

One problem is that the code to switch to an alternate parent was
running in PRE_RATE_CHANGE.  ...and the code to switch to slow mode
was _also_ running in PRE_RATE_CHANGE.  That meant there was no real
guarantee that we would switch to an alternate parent before switching
to 24MHz mode.

Let's move the switch to "slow mode" straight into
rockchip_rk3066_pll_set_rate().  That means we're guaranteed that the
24MHz is really a last-resort.

Note that without this change on real systems we were the code to
switch to an alternate parent at 24MHz.  In some older versions of
that code we'd appy a (temporary) / 5 to the 24MHz causing us to run
at 4.8MHz.  That wasn't enough to service USB interrupts in some cases
and could lead to a system hang.
Signed-off-by: NDoug Anderson <dianders@chromium.org>
Signed-off-by: NHeiko Stuebner <heiko@sntech.de>

Signed-off-by: NHeiko Stuebner <heiko@sntech.de>
Reviewed-by: NDoug Anderson <dianders@chromium.org>

The MBUS clock on sun8i is slightly different from the old mod0 clocks.
The divider is 3 bits wider, while also needing a divider table for the
higher 4 values, which all set the same divider.
Signed-off-by: NChen-Yu Tsai <wens@csie.org>
Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>

The MMC clock we thought we had until now are actually not one but three
different clocks.

The main one is unchanged, and will have three outputs:
  - The clock fed into the MMC
  - a sample and output clocks, to deal with when should we output/sample data
    to/from the MMC bus

The phase control we had are actually controlling the two latter clocks, but
the main MMC one is unchanged.

We can adjust the phase with a 3 bits value, from 0 to 7, 0 meaning a 180 phase
shift, and the other values being the number of periods from the MMC parent
clock to outphase the clock of.
Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>
Acked-by: NHans de Goede <hdegoede@redhat.com>

Move the MBUS clock to the module clocks file. It's pretty trivial, but still
requires to enable the clocks to make sure it won't get disabled.
Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>
Acked-by: NHans de Goede <hdegoede@redhat.com>

Since we know have the ability to declare factors clock outside of clk-sunxi,
create a new mod0 driver to deal with the mod0 clocks.
Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>
Acked-by: NHans de Goede <hdegoede@redhat.com>

Now that we have a compatible of its own for the mbus clock, switch to it.
Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>
Acked-by: NHans de Goede <hdegoede@redhat.com>

Even though the mbus clock is a regular module clock, given its nature, it
needs to be enabled all the time.

Introduce a new compatible, to differentiate it from the other module clocks.
Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>
Acked-by: NHans de Goede <hdegoede@redhat.com>

Until now, the factors clock probing was done directly by sunxi_init_clocks,
with the factors registration being called directly with the clocks data passed
as an argument.

This approch has shown its limits when we added more clocks, since we couldn't
really split code with such a logic in smaller files, and led to a huge file
having all the clocks.

Introduce an intermediate probing function, so that factor clocks will be able
to directly be called by CLK_OF_DECLARE, which will in turn ease the split into
several files.
Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>
Acked-by: NHans de Goede <hdegoede@redhat.com>

The current phase API doesn't look into the actual hardware to get the phase
value, but will rather get it from a variable only set by the set_phase
function.

This will cause issue when the client driver will never call the set_phase
function, where we can end up having a reported phase that will not match what
the hardware has been programmed to by the bootloader or what phase is
programmed out of reset.

Add a new get_phase function for the drivers to implement so that we can get
this value.
Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>
Reviewed-by: NHeiko Stuebner <heiko@sntech.de>
Acked-by: NHans de Goede <hdegoede@redhat.com>

CLK_OF_DECLARE relies on OF_DECLARE_1 that is defined in of.h. Fixes build
errors when one use CLK_OF_DECLARE but doesn't include of.h
Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>
Acked-by: NHans de Goede <hdegoede@redhat.com>

A common operation for a clock signal generator is to shift the phase of
that signal. This patch introduces a new function to the clk.h API to
dynamically adjust the phase of a clock signal. Additionally this patch
introduces support for the new function in the common clock framework
via the .set_phase call back in struct clk_ops.
Signed-off-by: NMike Turquette <mturquette@linaro.org>
Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>
Reviewed-by: NHeiko Stuebner <heiko@sntech.de>
Acked-by: NHans de Goede <hdegoede@redhat.com>

clock changes for mvebu for v3.18

 - correct timer drift caused by SSCG deviation
 - fix typo in comment

The added gpio-gate-clock is a basic clock that can be enabled and
disabled trough a gpio output. The DT binding document for the clock
is also added. For EPROBE_DEFER handling the registering of the clock
has to be delayed until of_clk_get() call time.
Signed-off-by: NJyri Sarha <jsarha@ti.com>
Signed-off-by: NMike Turquette <mturquette@linaro.org>

Merge tag 'qcom-clocks-for-3.18' of git://git.kernel.org/pub/scm/linux/kernel/git/galak/linux-qcom into clk-next

qcom clock changes for 3.18

Some fixes for the IPQ driver and some code consolidation
and refactoring.

Tegra clk updates for 3.18

If CONFIG_COMMON_CLK is selected then __clk_get and __clk_put are
defined in drivers/clk/clk.c and declared in include/linux/clkdev.h.

Sylwester's series[0] to properly support clk_{get,put} in the common
clock framework made changes to the asm-specific clkdev.h headers, but
not the asm-generic version. Tomeu's recent changes[1] to introduce a
provider/consumer split in the clock framework uncovered this problem,
causing the following build error on any architecture using the
asm-generic clkdev.h (e.g. x86 architecture and the ACPI LPSS driver):

In file included from drivers/acpi/acpi_lpss.c:15:0:
include/linux/clkdev.h:59:5: error: conflicting types for ‘__clk_get’
 int __clk_get(struct clk_core *clk);
     ^
In file included from arch/x86/include/generated/asm/clkdev.h:1:0,
                 from include/linux/clkdev.h:15,
                 from drivers/acpi/acpi_lpss.c:15:
include/asm-generic/clkdev.h:20:19: note: previous definition of ‘__clk_get’ was here
 static inline int __clk_get(struct clk *clk) { return 1; }
                   ^

Fixed by only declarating  __clk_get and __clk_put when
CONFIG_COMMON_CLK is set.

[0] http://lkml.kernel.org/r/<1386177127-2894-5-git-send-email-s.nawrocki@samsung.com>
[1] http://lkml.kernel.org/r/<1409758148-20104-1-git-send-email-tomeu.vizoso@collabora.com>
Signed-off-by: NMike Turquette <mturquette@linaro.org>

There is no need to init .owner field.

Based on the patch from Peter Griffin <peter.griffin@linaro.org>
"mmc: remove .owner field for drivers using module_platform_driver"

This patch removes the superflous .owner field for drivers which
use the module_platform_driver API, as this is overriden in
platform_driver_register anyway."
Signed-off-by: NKiran Padwal <kiran.padwal@smartplayin.com>
Signed-off-by: NMike Turquette <mturquette@linaro.org>

This patch add the clock node in PD_VIDEO
Signed-off-by: NKever Yang <kever.yang@rock-chips.com>
Reviewed-by: NHeiko Stuebner <heiko@sntech.de>
Reviewed-by: NDoug Anderson <dianders@chromium.org>
Tested-by: NDoug Anderson <dianders@chromium.org>
Signed-off-by: NMike Turquette <mturquette@linaro.org>

This patch use the new defined clock ID to initial the clock nodes.
Signed-off-by: NKever Yang <kever.yang@rock-chips.com>
Reviewed-by: NDoug Anderson <dianders@chromium.org>
Reviewed-by: NHeiko Stuebner <heiko@sntech.de>
Signed-off-by: NMike Turquette <mturquette@linaro.org>

This patch add some clock binding id for different modules
that under development and going to send upstream.
Signed-off-by: NKever Yang <kever.yang@rock-chips.com>
Reviewed-by: NHeiko Stuebner <heiko@sntech.de>
Signed-off-by: NMike Turquette <mturquette@linaro.org>

The npll on rk3288 is exactly the same pll type as the other 4. Yet it
was missing the link to the rate table, making rate changes impossible.
Change that by setting the table.
Signed-off-by: NHeiko Stuebner <heiko@sntech.de>
Reviewed-by: NDoug Anderson <dianders@chromium.org>
Tested-by: NDoug Anderson <dianders@chromium.org>
Tested-by: NKever Yang <kever.yang@rock-chips.com>
Signed-off-by: NMike Turquette <mturquette@linaro.org>

The rk3288 actually has 12 softresets, so fix the register count.
Signed-off-by: NMark yao <mark.yao@rock-chips.com>
Reviewed-by: NHeiko Stuebner <heiko@sntech.de>
Reviewed-by: NDoug Anderson <dianders@chromium.org>
Signed-off-by: NMike Turquette <mturquette@linaro.org>

The patch add the rest of the indices of the additional reset
registers from the updated TRM.
Signed-off-by: NMark yao <mark.yao@rock-chips.com>
Reviewed-by: NDoug Anderson <dianders@chromium.org>
Signed-off-by: NMike Turquette <mturquette@linaro.org>

The banked MD RCGs in global clock control have a different
register layout than the ones implemented in multimedia clock
control. Add support for these types of clocks so we can change
the rates of the UBI32 clocks.
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

Some PLLs may require changing their rate at runtime. Add support
for these PLLs.
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

There are two find_freq() functions in clk-rcg.c and clk-rcg2.c
that are almost exactly the same. Consolidate them into one
function to save on some code space.

Cc: Mike Turquette <mturquette@linaro.org>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

This patch adds the PLL0 that is required for the USB clocks to
work properly.
Signed-off-by: NAndy Gross <agross@codeaurora.org>
Fixes: 24d8fba4 "clk: qcom: Add support for IPQ8064's global clock controller (GCC)"
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

Don't abort clock initialization if we cannot match an entry in
tegra_clk_init_table to a valid entry in the clk array.

Also log a corresponding error message.

This was discovered when testing a patch that removed the EMC clock from
tegra124_clks but left a mention in tegra_clk_init_table.
Signed-off-by: NTomeu Vizoso <tomeu.vizoso@collabora.com>
Reviewed-by: NStephen Warren <swarren@nvidia.com>

These clocks are used as parents for some EMC timings.
Signed-off-by: NMikko Perttunen <mperttunen@nvidia.com>