- 02 7月, 2013 3 次提交
-
-
由 Alex Deucher 提交于
Bad pointer math. Fixes hangs in state transitions with BTC+ asics. Signed-off-by: NAlex Deucher <alexander.deucher@amd.com> -
由 Alex Deucher 提交于
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com> -
由 Alex Deucher 提交于
Function doesn't do anything useful. Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
-
- 01 7月, 2013 37 次提交
-
-
由 Dave Airlie 提交于
Merge branch 'drm-nouveau-next' of git://anongit.freedesktop.org/git/nouveau/linux-2.6 into drm-next - Various fixes that make surviving concurrent piglit more possible. - Buffer object deletion no longer synchronous - Context/register initialisation updates that have been reported to solve some stability issues (particularly on some problematic GF119 chips) - Kernel side support for VP2 video decoding engines * 'drm-nouveau-next' of git://anongit.freedesktop.org/git/nouveau/linux-2.6: (44 commits) drm/nvd0-/disp: handle case where display engine is missing/disabled drm/gr/nvc0-: merge nvc0/nve0 ucode, and use cpp instead of m4 drm/nouveau/bsp/nv84: initial vp2 engine implementation drm/nouveau/vp/nv84: initial vp2 engine implementation drm/nouveau/core: xtensa engine base class implementation drm/nouveau/vdec: fork vp3 implementations from vp2 drm/nouveau/core: move falcon class to engine/ drm/nouveau/kms: don't fail if there's no dcb table entries drm/nouveau: remove limit on gart drm/nouveau/vm: perform a bar flush when flushing vm drm/nvc0/gr: cleanup register lists, and add nvce/nvcf to switches drm/nvc8/gr: update initial register/context values drm/nvc4/gr: update initial register/context values drm/nvc1/gr: update initial register/context values drm/nvc3/gr: update initial register/context values drm/nvc0/gr: update initial register/context values drm/nvd9/gr: update initial register/context values drm/nve4/gr: update initial register/context values drm/nvc0-/gr: bump maximum gpc/tpc limits drm/nvf0/gr: initial register/context setup ...
-
由 Maarten Lankhorst 提交于
Signed-off-by: NBen Skeggs <bskeggs@redhat.com> -
由 Ben Skeggs 提交于
No code changes, proven by envyas producing identical binaries. Signed-off-by: NBen Skeggs <bskeggs@redhat.com> -
由 Ilia Mirkin 提交于
Signed-off-by: NIlia Mirkin <imirkin@alum.mit.edu> Signed-off-by: NBen Skeggs <bskeggs@redhat.com>
-
由 Ilia Mirkin 提交于
Signed-off-by: NIlia Mirkin <imirkin@alum.mit.edu> Signed-off-by: NBen Skeggs <bskeggs@redhat.com>
-
由 Ilia Mirkin 提交于
Signed-off-by: NIlia Mirkin <imirkin@alum.mit.edu> Signed-off-by: NBen Skeggs <bskeggs@redhat.com>
-
由 Ilia Mirkin 提交于
Signed-off-by: NIlia Mirkin <imirkin@alum.mit.edu> Signed-off-by: NBen Skeggs <bskeggs@redhat.com>
-
由 Ben Skeggs 提交于
Not really "core" per-se. About to merge Ilia's work adding another similar class for the VP2 xtensa engines, so, seems like a good time to move all these to engine/. Signed-off-by: NBen Skeggs <bskeggs@redhat.com> -
由 Ben Skeggs 提交于
Fixes module not loading on Tesla K20. Signed-off-by: NBen Skeggs <bskeggs@redhat.com> -
由 Maarten Lankhorst 提交于
Most graphics cards nowadays have a multiple of this limit as their vram, so limiting GART doesn't seem to make much sense. Signed-off-by: NMaarten >Lnkhorst <maarten.lankhorst@canonical.com> Signed-off-by: NBen Skeggs <bskeggs@redhat.com>
-
由 Maarten Lankhorst 提交于
Appears to fix the regression from "drm/nvc0/vm: handle bar tlb flushes internally". nvidia always seems to do this flush after writing values. Signed-off-by: NMaarten Lankhorst <maarten.lankhorst@canonical.com> Signed-off-by: NBen Skeggs <bskeggs@redhat.com>
-
由 Ben Skeggs 提交于
Signed-off-by: NBen Skeggs <bskeggs@redhat.com> -
由 Ben Skeggs 提交于
Signed-off-by: NBen Skeggs <bskeggs@redhat.com> -
由 Ben Skeggs 提交于
Signed-off-by: NBen Skeggs <bskeggs@redhat.com> -
由 Ben Skeggs 提交于
Signed-off-by: NBen Skeggs <bskeggs@redhat.com> -
由 Ben Skeggs 提交于
Signed-off-by: NBen Skeggs <bskeggs@redhat.com> -
由 Ben Skeggs 提交于
Signed-off-by: NBen Skeggs <bskeggs@redhat.com> -
由 Ben Skeggs 提交于
Signed-off-by: NBen Skeggs <bskeggs@redhat.com> -
由 Ben Skeggs 提交于
Signed-off-by: NBen Skeggs <bskeggs@redhat.com> -
由 Ben Skeggs 提交于
Needed for GK110, separate commit to catch any unexpected breaks to other parts of the code. Signed-off-by: NBen Skeggs <bskeggs@redhat.com> -
由 Ben Skeggs 提交于
Signed-off-by: NBen Skeggs <bskeggs@redhat.com> -
由 Ben Skeggs 提交于
Signed-off-by: NBen Skeggs <bskeggs@redhat.com> -
由 Ben Skeggs 提交于
Signed-off-by: NBen Skeggs <bskeggs@redhat.com> -
由 Ben Skeggs 提交于
As opposed to an explicit wait. Allows userspace to not stall waiting on buffer deletion. Signed-off-by: NBen Skeggs <bskeggs@redhat.com> -
由 Ben Skeggs 提交于
Signed-off-by: NBen Skeggs <bskeggs@redhat.com> -
由 Ben Skeggs 提交于
Signed-off-by: NBen Skeggs <bskeggs@redhat.com> -
由 Ben Skeggs 提交于
nvc0_vm_flush() accesses the pgd list, which will soon be able to race with vm_unlink() during channel destruction. Signed-off-by: NBen Skeggs <bskeggs@redhat.com> -
由 Ben Skeggs 提交于
Signed-off-by: NBen Skeggs <bskeggs@redhat.com> -
由 Ben Skeggs 提交于
These operations can take quite some time, and we really don't want to have to hold a spinlock for too long. Now that the lock ordering for vm and the gr/nv84 hw bug workaround has been reversed, it's possible to use a mutex here. Signed-off-by: NBen Skeggs <bskeggs@redhat.com> -
由 Ben Skeggs 提交于
This reverses the lock ordering between VM and gr/nv84:nvc0. Signed-off-by: NBen Skeggs <bskeggs@redhat.com> -
由 Ben Skeggs 提交于
Signed-off-by: NBen Skeggs <bskeggs@redhat.com> -
由 Ben Skeggs 提交于
Signed-off-by: NBen Skeggs <bskeggs@redhat.com> -
由 Ben Skeggs 提交于
Signed-off-by: NBen Skeggs <bskeggs@redhat.com> -
由 Ben Skeggs 提交于
NVIDIA's name... Signed-off-by: NBen Skeggs <bskeggs@redhat.com> -
由 Ben Skeggs 提交于
Signed-off-by: NBen Skeggs <bskeggs@redhat.com> -
由 Ben Skeggs 提交于
Helps us to get identical numbers to the binary driver for (at least) Kepler memory PLLs, and fixes a rounding error. Signed-off-by: NBen Skeggs <bskeggs@redhat.com> -
由 Ben Skeggs 提交于
Signed-off-by: NBen Skeggs <bskeggs@redhat.com>
-