1. 09 6月, 2006 1 次提交
    • A
      [PATCH] Fix HPET operation on 32-bit NVIDIA platforms · d44647b0
      Andy Currid 提交于
      From: "Andy Currid" <ACurrid@nvidia.com>
      
      This patch fixes a kernel panic during boot that occurs on NVIDIA platforms
      that have HPET enabled.
      
      When HPET is enabled, the standard timer IRQ is routed to IOAPIC pin 2 and is
      advertised as such in the ACPI APIC table - but an earlier workaround in the
      kernel was ignoring this override.  The fix is to honor timer IRQ overrides
      from ACPI when HPET is detected on an NVIDIA platform.
      Signed-off-by: NAndy Currid <acurrid@nvidia.com>
      Cc: "Brown, Len" <len.brown@intel.com>
      Cc: "Yu, Luming" <luming.yu@intel.com>
      Cc: Andi Kleen <ak@muc.de>
      Signed-off-by: NAndrew Morton <akpm@osdl.org>
      Signed-off-by: NLinus Torvalds <torvalds@osdl.org>
      d44647b0
  2. 31 5月, 2006 1 次提交
  3. 16 5月, 2006 1 次提交
  4. 04 5月, 2006 1 次提交
  5. 02 5月, 2006 1 次提交
  6. 19 4月, 2006 1 次提交
  7. 11 4月, 2006 1 次提交
  8. 10 4月, 2006 1 次提交
  9. 27 3月, 2006 1 次提交
  10. 09 3月, 2006 1 次提交
    • A
      [PATCH] i386: port ATI timer fix from x86_64 to i386 II · f9262c12
      Andi Kleen 提交于
      ATI chipsets tend to generate double timer interrupts for the local APIC
      timer when both the 8254 and the IO-APIC timer pins are enabled.  This is
      because they route it to both and the result is anded together and the CPU
      ends up processing it twice.
      
      This patch changes check_timer to disable the 8254 routing for interrupt 0.
      
      I think it would be safe on all chipsets actually (i tested it on a couple
      and it worked everywhere) and Windows seems to do it in a similar way, but
      to be conservative this patch only enables this mode on ATI (and adds
      options to enable/disable too)
      
      Ported over from a similar x86-64 change.
      
      I reused the ACPI earlyquirk infrastructure for the ATI bridge check, but
      tweaked it a bit to work even without ACPI.
      
      Inspired by a patch from Chuck Ebbert, but redone.
      
      Cc: Chuck Ebbert <76306.1226@compuserve.com>
      Cc: "Brown, Len" <len.brown@intel.com>
      Signed-off-by: NAndrew Morton <akpm@osdl.org>
      Signed-off-by: NLinus Torvalds <torvalds@osdl.org>
      f9262c12
  11. 28 2月, 2006 1 次提交
  12. 27 2月, 2006 1 次提交
  13. 05 2月, 2006 1 次提交
  14. 12 1月, 2006 1 次提交
  15. 28 12月, 2005 1 次提交
  16. 01 12月, 2005 2 次提交
  17. 21 11月, 2005 1 次提交
  18. 15 11月, 2005 2 次提交
    • S
      [PATCH] x86_64: Unmap NULL during early bootup · f6c2e333
      Siddha, Suresh B 提交于
      We should zap the low mappings, as soon as possible, so that we can catch
      kernel bugs more effectively. Previously early boot had NULL mapped
      and didn't trap on NULL references.
      
      This patch introduces boot_level4_pgt, which will always have low identity
      addresses mapped.  Druing boot, all the processors will use this as their
      level4 pgt.  On BP, we will switch to init_level4_pgt as soon as we enter C
      code and zap the low mappings as soon as we are done with the usage of
      identity low mapped addresses.  On AP's we will zap the low mappings as
      soon as we jump to C code.
      Signed-off-by: NSuresh Siddha <suresh.b.siddha@intel.com>
      Signed-off-by: NAshok Raj <ashok.raj@intel.com>
      Signed-off-by: NAndi Kleen <ak@suse.de>
      Signed-off-by: NLinus Torvalds <torvalds@osdl.org>
      f6c2e333
    • J
      [PATCH] i386/x86-64: Share interrupt vectors when there is a large number of interrupt sources · 6004e1b7
      James Cleverdon 提交于
      Here's a patch that builds on Natalie Protasevich's IRQ compression
      patch and tries to work for MPS boots as well as ACPI.  It is meant for
      a 4-node IBM x460 NUMA box, which was dying because it had interrupt
      pins with GSI numbers > NR_IRQS and thus overflowed irq_desc.
      
      The problem is that this system has 270 GSIs (which are 1:1 mapped with
      I/O APIC RTEs) and an 8-node box would have 540.  This is much bigger
      than NR_IRQS (224 for both i386 and x86_64).  Also, there aren't enough
      vectors to go around.  There are about 190 usable vectors, not counting
      the reserved ones and the unused vectors at 0x20 to 0x2F.  So, my patch
      attempts to compress the GSI range and share vectors by sharing IRQs.
      
      Cc: "Protasevich, Natalie" <Natalie.Protasevich@unisys.com>
      Signed-off-by: NAndi Kleen <ak@suse.de>
      Signed-off-by: NLinus Torvalds <torvalds@osdl.org>
      6004e1b7
  19. 01 10月, 2005 1 次提交
  20. 27 9月, 2005 1 次提交
  21. 15 9月, 2005 1 次提交
  22. 13 9月, 2005 2 次提交
  23. 11 9月, 2005 1 次提交
  24. 05 9月, 2005 1 次提交
  25. 26 8月, 2005 1 次提交
  26. 25 8月, 2005 3 次提交
  27. 05 8月, 2005 3 次提交
  28. 12 7月, 2005 2 次提交
  29. 28 6月, 2005 2 次提交
    • G
      [PATCH] PCI: add proper MCFG table parsing to ACPI core. · 54549391
      Greg Kroah-Hartman 提交于
      This patch is the first step in properly handling the MCFG PCI table.
      It defines the structures properly, and saves off the table so that the
      pci mmconfig code can access it.  It moves the parsing of the table a
      little later in the boot process, but still before the information is
      needed.
      Signed-off-by: NGreg Kroah-Hartman <gregkh@suse.de>
      54549391
    • K
      [PATCH] ACPI based I/O APIC hot-plug: add interfaces · b1bb248a
      Kenji Kaneshige 提交于
      This patch adds the following new interfaces for I/O xAPIC
      hotplug. The implementation of these interfaces depends on each
      architecture.
      
          o int acpi_register_ioapic(acpi_handle handle, u64 phys_addr,
      			       u32 gsi_base);
      
              This new interface is to add a new I/O xAPIC specified by
              phys_addr and gsi_base pair. phys_addr is the physical address
              to which the I/O xAPIC is mapped and gsi_base is global system
              interrupt base of the I/O xAPIC. acpi_register_ioapic returns
              0 on success, or negative value on error.
      
          o int acpi_unregister_ioapic(acpi_handle handle, u32 gsi_base);
      
              This new interface is to remove a I/O xAPIC specified by
              gsi_base. acpi_unregister_ioapic returns 0 on success, or
              negative value on error.
      Signed-off-by: NKenji Kaneshige <kaneshige.kenji@jp.fujitsu.com>
      Signed-off-by: NAndrew Morton <akpm@osdl.org>
      Signed-off-by: NGreg Kroah-Hartman <gregkh@suse.de>
      b1bb248a
  30. 26 6月, 2005 2 次提交