All of the regular CPU init path needs to be __cpuinit annotated for CPU
hotplug.
Signed-off-by: NPaul Mundt <lethal@linux-sh.org>

This does a detect_cpu_and_cache_system() -> cpu_probe() rename, tidies
up the unused return value, and stuffs it under __cpuinit in preparation
for CPU hotplug.
Signed-off-by: NPaul Mundt <lethal@linux-sh.org>

This follows the x86 change and kills off the unthrottle stub. As the x86
change killed off the generic callback it isn't used anymore anyways.
Signed-off-by: NPaul Mundt <lethal@linux-sh.org>

This zeroes out the number of cache aliases in the cache info descriptors
when hardware alias avoidance is enabled. This cuts down on the amount of
flushing taken care of by common code, and also permits coherency control
to be disabled for the single CPU and 4k page size case.
Signed-off-by: NPaul Mundt <lethal@linux-sh.org>

Previously the struct module definition was pulled in from other headers,
but we want the reference to be explicit. Fixes up randconfig build
issues.
Signed-off-by: NPaul Mundt <lethal@linux-sh.org>

This enables support for the hardware synonym avoidance handling on SH-X3
CPUs for the case where dcache aliases are possible. icache handling is
retained, but we flip on broadcasting of the block invalidations due to
the lack of coherency otherwise on SMP.
Signed-off-by: NPaul Mundt <lethal@linux-sh.org>

This wires up power-off support for the SDK7786 board.
Signed-off-by: NPaul Mundt <lethal@linux-sh.org>

This implements support for hardware-managed IRQ balancing as implemented
by SH-X3 cores (presently only hooked up for SH7786, but can probably be
carried over to other SH-X3 cores, too).

CPUs need to specify their distribution register along with the mask
definitions, as these follow the same format. Peripheral IRQs that don't
opt out of balancing will be automatically distributed at the whim of the
hardware block, while each CPU needs to verify whether it is handling the
IRQ or not, especially before clearing the mask.
Signed-off-by: NPaul Mundt <lethal@linux-sh.org>

Make sure that the timer IRQs and IPIs aren't enabled for IRQ balancing.
IPIs are disabled as a result of being percpu while the timers simply
disable balancing outright.
Signed-off-by: NPaul Mundt <lethal@linux-sh.org>

This adds support for hardware-assisted userspace irq masking for
special priority levels. Due to the SR.IMASK interactivity, only some
platforms implement this in hardware (including but not limited to
SH-4A interrupt controllers, and ARM-based SH-Mobile CPUs). Each CPU
needs to wire this up on its own, for now only SH7786 is wired up as an
example.
Signed-off-by: NPaul Mundt <lethal@linux-sh.org>

Hook up DMAC0 on SH7786.
Signed-off-by: NPaul Mundt <lethal@linux-sh.org>

Presently address translation is default-enabled regardless of whether
CONFIG_MMU is set or not in the SH-4 case, this fixes it up, and also
makes the control init word a bit more readable in the process.
Signed-off-by: NPaul Mundt <lethal@linux-sh.org>

We provide regs->tstate, regs->tpc, regs->tnpc and
regs->u_regs[UREG_FP].

regs->tstate is necessary for:

	user_mode()		(via perf_exclude_event())

	perf_misc_flags()	(via perf_prepare_sample())

regs->tpc is necessary for:

	perf_instruction_pointer() (via perf_prepare_sample())

and regs->u_regs[UREG_FP] is necessary for:

	perf_callchain()	(via perf_prepare_sample())

The regs->tnpc value is provided just to be tidy.
Signed-off-by: NDavid S. Miller <davem@davemloft.net>

Signed-off-by: NDavid S. Miller <davem@davemloft.net>

vmemmap_populate() attempts to report the used index and total size of
vmemmap_table, but it wrongly shifts the total size so that it is
always shown as 0.
Signed-off-by: NBen Hutchings <ben@decadent.org.uk>
Signed-off-by: NDavid S. Miller <davem@davemloft.net>

Now that software events use perf_arch_fetch_caller_regs() too, we
need the powerpc version to be always built.

Fixes the following build error:

	(.text+0x3210): undefined reference to `perf_arch_fetch_caller_regs'
	(.text+0x3324): undefined reference to `perf_arch_fetch_caller_regs'
	(.text+0x33bc): undefined reference to `perf_arch_fetch_caller_regs'
	(.text+0x33ec): undefined reference to `perf_arch_fetch_caller_regs'
	(.text+0xd4a0): undefined reference to `perf_arch_fetch_caller_regs'
	arch/powerpc/kernel/built-in.o:(.text+0xd528): more undefined references to `perf_arch_fetch_caller_regs' follow
	make[1]: *** [.tmp_vmlinux1] Error 1
	make: *** [sub-make] Error 2
Reported-by: NMichael Ellerman <michael@ellerman.id.au>
Reported-by: NIngo Molnar <mingo@elte.hu>
Signed-off-by: NFrederic Weisbecker <fweisbec@gmail.com>
Cc: Peter Zijlstra <a.p.zijlstra@chello.nl>
Cc: Arnaldo Carvalho de Melo <acme@redhat.com>
Cc: Paul Mackerras <paulus@samba.org>

When profiling a 32-bit process on a 64-bit kernel, callgraph tracing
stopped after the first function, because it has seen a garbage memory
address (tried to interpret the frame pointer, and return address as a
64-bit pointer).

Fix this by using a struct stack_frame with 32-bit pointers when the
TIF_IA32 flag is set.

Note that TIF_IA32 flag must be used, and not is_compat_task(), because
the latter is only set when the 32-bit process is executing a syscall,
which may not always be the case (when tracing page fault events for
example).
Signed-off-by: NTörök Edwin <edwintorok@gmail.com>
Signed-off-by: NPeter Zijlstra <a.p.zijlstra@chello.nl>
Acked-by: NFrederic Weisbecker <fweisbec@gmail.com>
Cc: "H. Peter Anvin" <hpa@zytor.com>
Cc: Paul Mackerras <paulus@samba.org>
Cc: x86@kernel.org
Cc: linux-kernel@vger.kernel.org
LKML-Reference: <1268820436-13145-1-git-send-email-edwintorok@gmail.com>
Signed-off-by: NIngo Molnar <mingo@elte.hu>

Commit 3f6da390 ("perf: Rework and fix the arch CPU-hotplug hooks") moved
the amd northbridge allocation from CPUS_ONLINE to CPUS_PREPARE_UP
however amd_nb_id() doesn't work yet on prepare so it would simply bail
basically reverting to a state where we do not properly track node wide
constraints - causing weird perf results.

Fix up the AMD NorthBridge initialization code by allocating from
CPU_UP_PREPARE and installing it from CPU_STARTING once we have the
proper nb_id. It also properly deals with the allocation failing.
Signed-off-by: NPeter Zijlstra <a.p.zijlstra@chello.nl>
[ robustify using amd_has_nb() ]
Signed-off-by: NStephane Eranian <eranian@google.com>
LKML-Reference: <1269353485.5109.48.camel@twins>
Signed-off-by: NIngo Molnar <mingo@elte.hu>

Because we need to have cpu identification things done by the time we run
CPU_STARTING notifiers.

( This init ordering will be relied on by the next fix. )
Signed-off-by: NPeter Zijlstra <a.p.zijlstra@chello.nl>
LKML-Reference: <1269353485.5109.48.camel@twins>
Signed-off-by: NIngo Molnar <mingo@elte.hu>

While the MMUCR.URB and ITLB/UTLB differentiation works fine for all SH-4
and later TLBs, these features are absent on SH-3. This splits out
local_flush_tlb_all() in to SH-4 and PTEAEX copies while restoring the
old SH-3 one, subsequently fixing up the build.

This will probably want some further reordering and tidying in the
future, but that's out of scope at present.
Signed-off-by: NPaul Mundt <lethal@linux-sh.org>

This is needed with some of the tracing code built as modules, so provide
the export.
Signed-off-by: NPaul Mundt <lethal@linux-sh.org>

Word copying is used only for aligned addresses.
Here is space for improving to use any better copying technique.
Look at memcpy implementation.
Signed-off-by: NMichal Simek <monstr@monstr.eu>

If early printk console is not enabled then all messages
are written to log buffer.
Signed-off-by: NMichal Simek <monstr@monstr.eu>

I forget to change register name in comments.
Signed-off-by: NMichal Simek <monstr@monstr.eu>

TLB size was hardcoded in asm code. This patch brings ability
to change TLB size only in one place. (mmu.h).
Signed-off-by: NMichal Simek <monstr@monstr.eu>

I forget to remove pci Kconfig option.
Signed-off-by: NMichal Simek <monstr@monstr.eu>

On the base on GCOV analytics is helpful to add likely/unlikely
macros.
Signed-off-by: NMichal Simek <monstr@monstr.eu>

Cachegrind analysis need this fix to be able to log asm functions.
Signed-off-by: NMichal Simek <monstr@monstr.eu>

To be able to do trace TLB operations.
Signed-off-by: NMichal Simek <monstr@monstr.eu>

Sync labels.
Signed-off-by: NMichal Simek <monstr@monstr.eu>

RESR and REAR uses the same regs in whole file.
Signed-off-by: NMichal Simek <monstr@monstr.eu>

This change synchronize register usage in code.
ESR = R4
EAR = R3
Signed-off-by: NMichal Simek <monstr@monstr.eu>

Any sync branch must follow mts instructions not mfs.
Signed-off-by: NMichal Simek <monstr@monstr.eu>

Disable debug option in asm code.
Signed-off-by: NMichal Simek <monstr@monstr.eu>

When the system has no lmb bram, main memory should be start from
zero because of microblaze vectors.

DTS fragment could look like:
	DDR2_SDRAM: memory@0 {
		device_type = "memory";
		reg = < 0x0 0x10000000 >;
	} ;

Then you have to setup CONFIG_KERNEL_BASE_ADDR=0 which caused
that kernel physical start address will be zero. On reset vector place
will be jump to 0x100 and on 0x100 starts kernel text.

You have to solve how to load the kernel before cpu starts.
Tested with XMD.
Signed-off-by: NMichal Simek <monstr@monstr.eu>

Last sync.
Signed-off-by: NMichal Simek <monstr@monstr.eu>

Move to generic location.
Signed-off-by: NMichal Simek <monstr@monstr.eu>

noMMU and MMU use them.
Signed-off-by: NMichal Simek <monstr@monstr.eu>

Here is small regression on dhrystone tests and I think
that on all benchmarking tests. It is due to better checking
mechanism in put_user macro
Signed-off-by: NMichal Simek <monstr@monstr.eu>

Use unified version.
Signed-off-by: NMichal Simek <monstr@monstr.eu>