1. 06 3月, 2019 1 次提交
    • J
      MIPS: BCM63XX: provide DMA masks for ethernet devices · 4a418a3d
      Jonas Gorski 提交于
      commit 18836b48ebae20850631ee2916d0cdbb86df813d upstream.
      
      The switch to the generic dma ops made dma masks mandatory, breaking
      devices having them not set. In case of bcm63xx, it broke ethernet with
      the following warning when trying to up the device:
      
      [    2.633123] ------------[ cut here ]------------
      [    2.637949] WARNING: CPU: 0 PID: 325 at ./include/linux/dma-mapping.h:516 bcm_enetsw_open+0x160/0xbbc
      [    2.647423] Modules linked in: gpio_button_hotplug
      [    2.652361] CPU: 0 PID: 325 Comm: ip Not tainted 4.19.16 #0
      [    2.658080] Stack : 80520000 804cd3ec 00000000 00000000 804ccc00 87085bdc 87d3f9d4 804f9a17
      [    2.666707]         8049cf18 00000145 80a942a0 00000204 80ac0000 10008400 87085b90 eb3d5ab7
      [    2.675325]         00000000 00000000 80ac0000 000022b0 00000000 00000000 00000007 00000000
      [    2.683954]         0000007a 80500000 0013b381 00000000 80000000 00000000 804a1664 80289878
      [    2.692572]         00000009 00000204 80ac0000 00000200 00000002 00000000 00000000 80a90000
      [    2.701191]         ...
      [    2.703701] Call Trace:
      [    2.706244] [<8001f3c8>] show_stack+0x58/0x100
      [    2.710840] [<800336e4>] __warn+0xe4/0x118
      [    2.715049] [<800337d4>] warn_slowpath_null+0x48/0x64
      [    2.720237] [<80289878>] bcm_enetsw_open+0x160/0xbbc
      [    2.725347] [<802d1d4c>] __dev_open+0xf8/0x16c
      [    2.729913] [<802d20cc>] __dev_change_flags+0x100/0x1c4
      [    2.735290] [<802d21b8>] dev_change_flags+0x28/0x70
      [    2.740326] [<803539e0>] devinet_ioctl+0x310/0x7b0
      [    2.745250] [<80355fd8>] inet_ioctl+0x1f8/0x224
      [    2.749939] [<802af290>] sock_ioctl+0x30c/0x488
      [    2.754632] [<80112b34>] do_vfs_ioctl+0x740/0x7dc
      [    2.759459] [<80112c20>] ksys_ioctl+0x50/0x94
      [    2.763955] [<800240b8>] syscall_common+0x34/0x58
      [    2.768782] ---[ end trace fb1a6b14d74e28b6 ]---
      [    2.773544] bcm63xx_enetsw bcm63xx_enetsw.0: cannot allocate rx ring 512
      
      Fix this by adding appropriate DMA masks for the platform devices.
      
      Fixes: f8c55dc6 ("MIPS: use generic dma noncoherent ops for simple noncoherent platforms")
      Signed-off-by: NJonas Gorski <jonas.gorski@gmail.com>
      Reviewed-by: NChristoph Hellwig <hch@lst.de>
      Reviewed-by: NFlorian Fainelli <f.fainelli@gmail.com>
      Signed-off-by: NPaul Burton <paul.burton@mips.com>
      Cc: linux-mips@linux-mips.org
      Cc: linux-kernel@vger.kernel.org
      Cc: Ralf Baechle <ralf@linux-mips.org>
      Cc: James Hogan <jhogan@kernel.org>
      Cc: stable@vger.kernel.org # v4.19+
      Signed-off-by: NGreg Kroah-Hartman <gregkh@linuxfoundation.org>
      4a418a3d
  2. 20 12月, 2017 1 次提交
  3. 30 7月, 2014 1 次提交
  4. 14 6月, 2013 1 次提交
    • F
      bcm63xx_enet: add support Broadcom BCM6345 Ethernet · 3dc6475c
      Florian Fainelli 提交于
      This patch adds support for the Broadcom BCM6345 SoC Ethernet. BCM6345
      has a slightly different and older DMA engine which requires the
      following modifications:
      
      - the width of the DMA channels on BCM6345 is 64 bytes vs 16 bytes,
        which means that the helpers enet_dma{c,s} need to account for this
        channel width and we can no longer use macros
      
      - BCM6345 DMA engine does not have any internal SRAM for transfering
        buffers
      
      - BCM6345 buffer allocation and flow control is not per-channel but
        global (done in RSET_ENETDMA)
      
      - the DMA engine bits are right-shifted by 3 compared to other DMA
        generations
      
      - the DMA enable/interrupt masks are a little different (we need to
        enabled more bits for 6345)
      
      - some register have the same meaning but are offsetted in the ENET_DMAC
        space so a lookup table is required to return the proper offset
      
      The MAC itself is identical and requires no modifications to work.
      Signed-off-by: NFlorian Fainelli <florian@openwrt.org>
      Acked-by: NRalf Baechle <ralf@linux-mips.org>
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      3dc6475c
  5. 11 6月, 2013 2 次提交
    • M
      bcm63xx_enet: add support for Broadcom BCM63xx integrated gigabit switch · 6f00a022
      Maxime Bizon 提交于
      Newer Broadcom BCM63xx SoCs: 6328, 6362 and 6368 have an integrated switch
      which needs to be driven slightly differently from the traditional
      external switches. This patch introduces changes in arch/mips/bcm63xx in order
      to:
      
      - register a bcm63xx_enetsw driver instead of bcm63xx_enet driver
      - update DMA channels configuration & state RAM base addresses
      - add a new platform data configuration knob to define the number of
        ports per switch/device and force link on some ports
      - define the required switch registers
      
      On the driver side, the following changes are required:
      
      - the switch ports need to be polled to ensure the link is up and
        running and RX/TX can properly work
      - basic switch configuration needs to be performed for the switch to
        forward packets to the CPU
      - update the MIB counters since the integrated
      Signed-off-by: NMaxime Bizon <mbizon@freebox.fr>
      Signed-off-by: NJonas Gorski <jogo@openwrt.org>
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      6f00a022
    • M
      bcm63xx_enet: split DMA channel register accesses · 0ae99b5f
      Maxime Bizon 提交于
      The current bcm63xx_enet driver always uses bcmenet_shared_base whenever
      it needs to access DMA channel configuration space or access the DMA
      channel state RAM. Split these register in 3 parts to be more accurate:
      
      - global DMA configuration
      - per DMA channel configuration space
      - per DMA channel state RAM space
      
      This is preliminary to support new chips where the global DMA
      configuration remains the same, but there is a varying number of DMA
      channels located at a different memory offset.
      Signed-off-by: NMaxime Bizon <mbizon@freebox.fr>
      Signed-off-by: NJonas Gorski <jogo@openwrt.org>
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      0ae99b5f
  6. 27 7月, 2010 1 次提交
  7. 18 9月, 2009 1 次提交