1. 09 5月, 2017 16 次提交
  2. 06 5月, 2017 2 次提交
    • A
      Revert "ARCv2: Allow enabling PAE40 w/o HIGHMEM" · cf4100d1
      Alexey Brodkin 提交于
      This reverts commit 7cab91b8.
      
      Now when we have a real hardware platform with PAE40 enabled
      (here I mean axs103 with firmware v1.2) and 1 Gb of DDR mapped to
      0x1_a000_0000-0x1_ffff_ffff we're really targeting memory above 4Gb
      when PAE40 is enabled. This in its turn requires HIGHMEM to be enabled
      otherwise user won't see any difference with enabling PAE in
      kernel configuration as only lowmem will be used anyways.
      Signed-off-by: NAlexey Brodkin <abrodkin@synopsys.com>
      Signed-off-by: NVineet Gupta <vgupta@synopsys.com>
      cf4100d1
    • V
      ARC: mm: fix build failure in linux-next for UP builds · 868a6530
      Vineet Gupta 提交于
      kisskb build service reported ARC defconfig build failures in linux-next
      
      | arch/arc/include/asm/mmu.h:75:21: error: 'NR_CPUS' undeclared here (not in a function)
      | make[3]: *** [arch/arc/mm/ioremap.o] Error 1
      | make[2]: *** [arch/arc/mm] Error 2
      | make[1]: *** [arch/arc] Error 2
      
      which I bisected to a subtle side-effect of a totally benign mm patch
      ("mm, vmalloc: properly track vmalloc users") which caused a header
      include chain deviation - asm/mmu.h using NR_CPUS before including
      linux/threads.h
      
      Fix that by adding the dependnet header and while it at fix a related
      header to include linux headers aheads of asm headers as sometimes that
      slso triggers such issues !
      
      Reported-by: noreply@ellerman.id.au
      Signed-off-by: NVineet Gupta <vgupta@synopsys.com>
      868a6530
  3. 05 5月, 2017 2 次提交
  4. 04 5月, 2017 2 次提交
  5. 03 5月, 2017 16 次提交
    • P
      Revert "KVM: Support vCPU-based gfn->hva cache" · 4e335d9e
      Paolo Bonzini 提交于
      This reverts commit bbd64115.
      
      I've been sitting on this revert for too long and it unfortunately
      missed 4.11.  It's also the reason why I haven't merged ring-based
      dirty tracking for 4.12.
      
      Using kvm_vcpu_memslots in kvm_gfn_to_hva_cache_init and
      kvm_vcpu_write_guest_offset_cached means that the MSR value can
      now be used to access SMRAM, simply by making it point to an SMRAM
      physical address.  This is problematic because it lets the guest
      OS overwrite memory that it shouldn't be able to touch.
      
      Cc: stable@vger.kernel.org
      Fixes: bbd64115Signed-off-by: NPaolo Bonzini <pbonzini@redhat.com>
      4e335d9e
    • N
      powerpc/64s: Power9 has no LPCR[VRMASD] field so don't set it · 700b7ead
      Nicholas Piggin 提交于
      Power9/ISAv3 has no VRMASD field in LPCR, we shouldn't be setting reserved bits,
      so don't set them on Power9.
      Signed-off-by: NNicholas Piggin <npiggin@gmail.com>
      Signed-off-by: NMichael Ellerman <mpe@ellerman.id.au>
      700b7ead
    • A
      powerpc/powernv: Fix TCE kill on NVLink2 · 6b3d12a9
      Alistair Popple 提交于
      Commit 616badd2 ("powerpc/powernv: Use OPAL call for TCE kill on
      NVLink2") forced all TCE kills to go via the OPAL call for
      NVLink2. However the PHB3 implementation of TCE kill was still being
      called directly from some functions which in some circumstances caused
      a machine check.
      
      This patch adds an equivalent IODA2 version of the function which uses
      the correct invalidation method depending on PHB model and changes all
      external callers to use it instead.
      
      Fixes: 616badd2 ("powerpc/powernv: Use OPAL call for TCE kill on NVLink2")
      Cc: stable@vger.kernel.org # v4.11+
      Signed-off-by: NAlistair Popple <alistair@popple.id.au>
      Signed-off-by: NMichael Ellerman <mpe@ellerman.id.au>
      6b3d12a9
    • M
      powerpc/mm/radix: Drop support for CPUs without lockless tlbie · 3c9ac2bc
      Michael Ellerman 提交于
      Currently the radix TLB code includes support for CPUs that do *not*
      have MMU_FTR_LOCKLESS_TLBIE. On those CPUs we are required to take a
      global spinlock before issuing a tlbie.
      
      Radix can only be built for 64-bit Book3s CPUs, and of those, only
      POWER4, 970, Cell and PA6T do not have MMU_FTR_LOCKLESS_TLBIE. Although
      it's possible to build a kernel with Radix support that can also boot on
      those CPUs, we happen to know that in reality none of those CPUs support
      the Radix MMU, so the code can never actually run on those CPUs.
      
      So remove the native_tlbie_lock in the Radix TLB code.
      
      Note that there is another lock of the same name in the hash code, which
      is unaffected by this patch.
      Reviewed-by: NNicholas Piggin <npiggin@gmail.com>
      Signed-off-by: NMichael Ellerman <mpe@ellerman.id.au>
      3c9ac2bc
    • B
      xen: Move xen_have_vector_callback definition to enlighten.c · 3dbd8204
      Boris Ostrovsky 提交于
      Commit 84d582d2 ("xen: Revert commits da72ff5b and
      72a9b186") defined xen_have_vector_callback in enlighten_hvm.c.
      Since guest-type-neutral code refers to this variable this causes
      build failures when CONFIG_XEN_PVHVM is not defined.
      
      Moving xen_have_vector_callback definition to enlighten.c resolves
      this issue.
      Signed-off-by: NBoris Ostrovsky <boris.ostrovsky@oracle.com>
      Reported-by: NRandy Dunlap <rdunlap@infradead.org>
      Acked-by: NRandy Dunlap <rdunlap@infradead.org>
      Reviewed-by: NJuergen Gross <jgross@suse.com>
      Signed-off-by: NJuergen Gross <jgross@suse.com>
      3dbd8204
    • M
      powerpc/book3s/mce: Move add_taint() later in virtual mode · d93b0ac0
      Mahesh Salgaonkar 提交于
      machine_check_early() gets called in real mode. The very first time when
      add_taint() is called, it prints a warning which ends up calling opal
      call (that uses OPAL_CALL wrapper) for writing it to console. If we get a
      very first machine check while we are in opal we are doomed. OPAL_CALL
      overwrites the PACASAVEDMSR in r13 and in this case when we are done with
      MCE handling the original opal call will use this new MSR on it's way
      back to opal_return. This usually leads to unexpected behaviour or the
      kernel to panic. Instead move the add_taint() call later in the virtual
      mode where it is safe to call.
      
      This is broken with current FW level. We got lucky so far for not getting
      very first MCE hit while in OPAL. But easily reproducible on Mambo.
      
      Fixes: 27ea2c42 ("powerpc: Set the correct kernel taint on machine check errors.")
      Cc: stable@vger.kernel.org # v4.2+
      Signed-off-by: NMahesh Salgaonkar <mahesh@linux.vnet.ibm.com>
      Signed-off-by: NMichael Ellerman <mpe@ellerman.id.au>
      d93b0ac0
    • M
      powerpc/sysfs: Move #ifdef CONFIG_HOTPLUG_CPU out of the function body · 3f2290e1
      Michael Ellerman 提交于
      The entire body of unregister_cpu_online() is inside an #ifdef
      CONFIG_HOTPLUG_CPU block. This is ugly and means we create an empty function
      when hotplug is disabled for no reason.
      
      Instead move the #ifdef out of the function body and define the function to be
      NULL in the else case. This means we'll pass NULL to cpuhp_setup_state(), but
      that's fine because it accepts NULL to mean there is no teardown callback, which
      is exactly what we want.
      Signed-off-by: NMichael Ellerman <mpe@ellerman.id.au>
      3f2290e1
    • M
      powerpc/smp: Document irq enable/disable after migrating IRQs · 687b8f24
      Michael Ellerman 提交于
      This code was until recently completely undocumented and even now the comment is
      not very verbose.
      
      We've already had one patch sent to remove the IRQ enable/disable because it's
      "paradoxical and unnecessary". So document it thoroughly to save anyone else
      from puzzling over it.
      Signed-off-by: NMichael Ellerman <mpe@ellerman.id.au>
      687b8f24
    • M
      powerpc/mpc52xx: Don't select user-visible RTAS_PROC · 0cc68bfa
      Michael Ellerman 提交于
      Otherwise we might select it when its dependenices aren't enabled,
      leading to a build break.
      
      It's default y anyway, so will be on unless someone disables it
      manually.
      Signed-off-by: NMichael Ellerman <mpe@ellerman.id.au>
      0cc68bfa
    • A
      powerpc/powernv: Document cxl dependency on special case in pnv_eeh_reset() · b7da1230
      Andrew Donnellan 提交于
      pnv_eeh_reset() has special handling for PEs whose primary bus is the
      root bus or the bus immediately underneath the root port.
      
      The cxl bi-modal card support added in b0b5e591 ("cxl: Add
      cxl_check_and_switch_mode() API to switch bi-modal cards") relies on
      this behaviour when hot-resetting the CAPI adapter following a mode
      switch.  Document this in pnv_eeh_reset() so we don't accidentally break
      it.
      Suggested-by: NGavin Shan <gwshan@linux.vnet.ibm.com>
      Signed-off-by: NAndrew Donnellan <andrew.donnellan@au1.ibm.com>
      Reviewed-by: NGavin Shan <gwshan@linux.vnet.ibm.com>
      Signed-off-by: NMichael Ellerman <mpe@ellerman.id.au>
      b7da1230
    • V
      ARCv2: mm: micro-optimize region flush generated code · f734a310
      Vineet Gupta 提交于
      DC_CTRL.RGN_OP is 3 bits wide, however only 1 bit is used in current
      programming model (0: flush, 1: invalidate)
      
      The current code targetting 3 bits leads to additional 8 byte AND
      operation which can be elided given that only 1 bit is ever set by
      software and/or looked at by hardware
      
      before
      ------
      
      | 80b63324 <__dma_cache_wback_inv_l1>:
      | 80b63324:	clri	r3
      | 80b63328:	lr	r2,[dc_ctrl]
      | 80b6332c:	and	r2,r2,0xfffff1ff	<--- 8 bytes insn
      | 80b63334:	or	r2,r2,576
      | 80b63338:	sr	r2,[dc_ctrl]
      | ...
      | ...
      | 80b63360 <__dma_cache_inv_l1>:
      | 80b63360:	clri	r3
      | 80b63364:	lr	r2,[dc_ctrl]
      | 80b63368:	and	r2,r2,0xfffff1ff	<--- 8 bytes insn
      | 80b63370:	bset_s	r2,r2,0x9
      | 80b63372:	sr	r2,[dc_ctrl]
      | ...
      | ...
      | 80b6338c <__dma_cache_wback_l1>:
      | 80b6338c:	clri	r3
      | 80b63390:	lr	r2,[dc_ctrl]
      | 80b63394:	and	r2,r2,0xfffff1ff	<--- 8 bytes insn
      | 80b6339c:	sr	r2,[dc_ctrl]
      
      after (AND elided totally in 2 cases, replaced with 2 byte BCLR in 3rd)
      -----
      
      | 80b63324 <__dma_cache_wback_inv_l1>:
      | 80b63324:	clri	r3
      | 80b63328:	lr	r2,[dc_ctrl]
      | 80b6332c:	or	r2,r2,576
      | 80b63330:	sr	r2,[dc_ctrl]
      | ...
      | ...
      | 80b63358 <__dma_cache_inv_l1>:
      | 80b63358:	clri	r3
      | 80b6335c:	lr	r2,[dc_ctrl]
      | 80b63360:	bset_s	r2,r2,0x9
      | 80b63362:	sr	r2,[dc_ctrl]
      | ...
      | ...
      | 80b6337c <__dma_cache_wback_l1>:
      | 80b6337c:	clri	r3
      | 80b63380:	lr	r2,[dc_ctrl]
      | 80b63384:	bclr_s	r2,r2,0x9
      | 80b63386:	sr	r2,[dc_ctrl]
      Signed-off-by: NVineet Gupta <vgupta@synopsys.com>
      f734a310
    • V
      ARCv2: mm: Merge 2 updates to DC_CTRL for region flush · ee40bd1e
      Vineet Gupta 提交于
      Region Flush has a weird programming model.
      
       1. Flush or Invalidate is selected by DC_CTRL.RGN_OP
       2 Flush-n-Invalidate is done by DC_CTRL.IM
      
      Given the code structuring before, case #2 above was generating two
      seperate updates to DC_CTRL which was pointless.
      
      | 80a342b0 <__dma_cache_wback_inv_l1>:
      | 80a342b0:	clri	r4
      | 80a342b4:	lr	r2,[dc_ctrl]
      | 80a342b8:	bset_s	r2,r2,0x6
      | 80a342ba:	sr	r2,[dc_ctrl]	<-- FIRST
      |
      | 80a342be:	bmskn	r3,r0,0x5
      |
      | 80a342c2:	lr	r2,[dc_ctrl]
      | 80a342c6:	and	r2,r2,0xfffff1ff
      | 80a342ce:	bset_s	r2,r2,0x9
      | 80a342d0:	sr	r2,[dc_ctrl]	<-- SECOND
      |
      | 80a342d4:	add_s	r1,r1,0x3f
      | 80a342d6:	bmsk_s	r0,r0,0x5
      | 80a342d8:	add_s	r0,r0,r1
      | 80a342da:	add_s	r0,r0,r3
      | 80a342dc:	sr	r0,[78]
      | 80a342e0:	sr	r3,[77]
      |...
      |...
      
      So move setting of DC_CTRL.RGN_OP into __before_dc_op() and combine with
      any other update.
      
      | 80b63324 <__dma_cache_wback_inv_l1>:
      | 80b63324:	clri	r3
      | 80b63328:	lr	r2,[dc_ctrl]
      | 80b6332c:	and	r2,r2,0xfffff1ff
      | 80b63334:	or	r2,r2,576
      | 80b63338:	sr	r2,[dc_ctrl]
      |
      | 80b6333c:	add_s	r1,r1,0x3f
      | 80b6333e:	bmskn	r2,r0,0x5
      | 80b63342:	add_s	r0,r0,r1
      | 80b63344:	sr	r0,[78]
      | 80b63348:	sr	r2,[77]
      Signed-off-by: NVineet Gupta <vgupta@synopsys.com>
      ee40bd1e
    • V
      ARCv2: mm: Implement cache region flush operations · 0d77117f
      Vineet Gupta 提交于
      These are more efficient than the per-line ops
      Signed-off-by: NVineet Gupta <vgupta@synopsys.com>
      0d77117f
    • V
      ARC: mm: Move full_page computation into cache version agnostic wrapper · 7d3d162b
      Vineet Gupta 提交于
      This reduces code duplication in each of cache version specific handlers
      Signed-off-by: NVineet Gupta <vgupta@synopsys.com>
      7d3d162b
    • D
      bpf, arm64: fix jit branch offset related to ldimm64 · ddc665a4
      Daniel Borkmann 提交于
      When the instruction right before the branch destination is
      a 64 bit load immediate, we currently calculate the wrong
      jump offset in the ctx->offset[] array as we only account
      one instruction slot for the 64 bit load immediate although
      it uses two BPF instructions. Fix it up by setting the offset
      into the right slot after we incremented the index.
      
      Before (ldimm64 test 1):
      
        [...]
        00000020:  52800007  mov w7, #0x0 // #0
        00000024:  d2800060  mov x0, #0x3 // #3
        00000028:  d2800041  mov x1, #0x2 // #2
        0000002c:  eb01001f  cmp x0, x1
        00000030:  54ffff82  b.cs 0x00000020
        00000034:  d29fffe7  mov x7, #0xffff // #65535
        00000038:  f2bfffe7  movk x7, #0xffff, lsl #16
        0000003c:  f2dfffe7  movk x7, #0xffff, lsl #32
        00000040:  f2ffffe7  movk x7, #0xffff, lsl #48
        00000044:  d29dddc7  mov x7, #0xeeee // #61166
        00000048:  f2bdddc7  movk x7, #0xeeee, lsl #16
        0000004c:  f2ddddc7  movk x7, #0xeeee, lsl #32
        00000050:  f2fdddc7  movk x7, #0xeeee, lsl #48
        [...]
      
      After (ldimm64 test 1):
      
        [...]
        00000020:  52800007  mov w7, #0x0 // #0
        00000024:  d2800060  mov x0, #0x3 // #3
        00000028:  d2800041  mov x1, #0x2 // #2
        0000002c:  eb01001f  cmp x0, x1
        00000030:  540000a2  b.cs 0x00000044
        00000034:  d29fffe7  mov x7, #0xffff // #65535
        00000038:  f2bfffe7  movk x7, #0xffff, lsl #16
        0000003c:  f2dfffe7  movk x7, #0xffff, lsl #32
        00000040:  f2ffffe7  movk x7, #0xffff, lsl #48
        00000044:  d29dddc7  mov x7, #0xeeee // #61166
        00000048:  f2bdddc7  movk x7, #0xeeee, lsl #16
        0000004c:  f2ddddc7  movk x7, #0xeeee, lsl #32
        00000050:  f2fdddc7  movk x7, #0xeeee, lsl #48
        [...]
      
      Also, add a couple of test cases to make sure JITs pass
      this test. Tested on Cavium ThunderX ARMv8. The added
      test cases all pass after the fix.
      
      Fixes: 8eee539d ("arm64: bpf: fix out-of-bounds read in bpf2a64_offset()")
      Reported-by: NDavid S. Miller <davem@davemloft.net>
      Signed-off-by: NDaniel Borkmann <daniel@iogearbox.net>
      Acked-by: NAlexei Starovoitov <ast@kernel.org>
      Cc: Xi Wang <xi.wang@gmail.com>
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      ddc665a4
    • D
      bpf, arm64: implement jiting of BPF_XADD · 85f68fe8
      Daniel Borkmann 提交于
      This work adds BPF_XADD for BPF_W/BPF_DW to the arm64 JIT and therefore
      completes JITing of all BPF instructions, meaning we can thus also remove
      the 'notyet' label and do not need to fall back to the interpreter when
      BPF_XADD is used in a program!
      
      This now also brings arm64 JIT in line with x86_64, s390x, ppc64, sparc64,
      where all current eBPF features are supported.
      
      BPF_W example from test_bpf:
      
        .u.insns_int = {
          BPF_ALU32_IMM(BPF_MOV, R0, 0x12),
          BPF_ST_MEM(BPF_W, R10, -40, 0x10),
          BPF_STX_XADD(BPF_W, R10, R0, -40),
          BPF_LDX_MEM(BPF_W, R0, R10, -40),
          BPF_EXIT_INSN(),
        },
      
        [...]
        00000020:  52800247  mov w7, #0x12 // #18
        00000024:  928004eb  mov x11, #0xffffffffffffffd8 // #-40
        00000028:  d280020a  mov x10, #0x10 // #16
        0000002c:  b82b6b2a  str w10, [x25,x11]
        // start of xadd mapping:
        00000030:  928004ea  mov x10, #0xffffffffffffffd8 // #-40
        00000034:  8b19014a  add x10, x10, x25
        00000038:  f9800151  prfm pstl1strm, [x10]
        0000003c:  885f7d4b  ldxr w11, [x10]
        00000040:  0b07016b  add w11, w11, w7
        00000044:  880b7d4b  stxr w11, w11, [x10]
        00000048:  35ffffab  cbnz w11, 0x0000003c
        // end of xadd mapping:
        [...]
      
      BPF_DW example from test_bpf:
      
        .u.insns_int = {
          BPF_ALU32_IMM(BPF_MOV, R0, 0x12),
          BPF_ST_MEM(BPF_DW, R10, -40, 0x10),
          BPF_STX_XADD(BPF_DW, R10, R0, -40),
          BPF_LDX_MEM(BPF_DW, R0, R10, -40),
          BPF_EXIT_INSN(),
        },
      
        [...]
        00000020:  52800247  mov w7,  #0x12 // #18
        00000024:  928004eb  mov x11, #0xffffffffffffffd8 // #-40
        00000028:  d280020a  mov x10, #0x10 // #16
        0000002c:  f82b6b2a  str x10, [x25,x11]
        // start of xadd mapping:
        00000030:  928004ea  mov x10, #0xffffffffffffffd8 // #-40
        00000034:  8b19014a  add x10, x10, x25
        00000038:  f9800151  prfm pstl1strm, [x10]
        0000003c:  c85f7d4b  ldxr x11, [x10]
        00000040:  8b07016b  add x11, x11, x7
        00000044:  c80b7d4b  stxr w11, x11, [x10]
        00000048:  35ffffab  cbnz w11, 0x0000003c
        // end of xadd mapping:
        [...]
      
      Tested on Cavium ThunderX ARMv8, test suite results after the patch:
      
        No JIT:   [ 3751.855362] test_bpf: Summary: 311 PASSED, 0 FAILED, [0/303 JIT'ed]
        With JIT: [ 3573.759527] test_bpf: Summary: 311 PASSED, 0 FAILED, [303/303 JIT'ed]
      Signed-off-by: NDaniel Borkmann <daniel@iogearbox.net>
      Acked-by: NAlexei Starovoitov <ast@kernel.org>
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      85f68fe8
  6. 02 5月, 2017 2 次提交