1. 23 3月, 2009 2 次提交
    • E
      [ARM] pxa: add base support for Marvell's PXA168 processor line · 49cbe786
      Eric Miao 提交于
      """The Marvell® PXA168 processor is the first in a family of application
      processors targeted at mass market opportunities in computing and consumer
      devices. It balances high computing and multimedia performance with low
      power consumption to support extended battery life, and includes a wealth
      of integrated peripherals to reduce overall BOM cost .... """
      
      See http://www.marvell.com/featured/pxa168.jsp for more information.
      
        1. Marvell Mohawk core is a hybrid of xscale3 and its own ARM core,
           there are many enhancements like instructions for flushing the
           whole D-cache, and so on
      
        2. Clock reuses Russell's common clkdev, and added the basic support
           for UART1/2.
      
        3. Devices are a bit different from the 'mach-pxa' way, the platform
           devices are now dynamically allocated only when necessary (i.e.
           when pxa_register_device() is called). Description for each device
           are stored in an array of 'struct pxa_device_desc'. Now that:
      
           a. this array of device description is marked with __initdata and
              can be freed up system is fully up
      
           b. which means board code has to add all needed devices early in
              his initializing function
      
           c. platform specific data can now be marked as __initdata since
              they are allocated and copied by platform_device_add_data()
      
        4. only the basic UART1/2/3 are added, more devices will come later.
      Signed-off-by: NJason Chagas <chagas@marvell.com>
      Signed-off-by: NEric Miao <eric.miao@marvell.com>
      49cbe786
    • E
      [ARM] pxa: introduce plat-pxa for PXA common code and add DMA support · bd5ce433
      Eric Miao 提交于
      1. introduce folder of 'arch/arm/plat-pxa' for common code across different
         PXA processor families
      
      2. initially moved DMA code into plat-pxa
      
      3. common code in <mach/dma.h> moved into <plat/dma.h>, new processors
         should implement its own <mach/dma.h>, provide the following required
         definitions and '#include <plat/dma.h>' in the end:
      
         - DMAC_REGS_VIRT for mapped virtual address of the DMA registers'
           physical I/O memory
      Signed-off-by: NEric Miao <eric.miao@marvell.com>
      bd5ce433
  2. 22 2月, 2009 1 次提交
  3. 12 2月, 2009 1 次提交
  4. 07 1月, 2009 1 次提交
  5. 21 12月, 2008 2 次提交
  6. 16 12月, 2008 1 次提交
  7. 14 12月, 2008 1 次提交
  8. 12 12月, 2008 1 次提交
  9. 10 12月, 2008 2 次提交
  10. 04 12月, 2008 1 次提交
  11. 01 12月, 2008 2 次提交
  12. 27 11月, 2008 6 次提交
  13. 23 10月, 2008 1 次提交
    • S
      ftrace: disable dynamic ftrace for all archs that use daemon · 07c4cc1c
      Steven Rostedt 提交于
      The ftrace daemon is complex and can cause nasty races if something goes
      wrong. Since it affects all of the kernel, this patch disables dynamic
      ftrace from any arch that depends on the daemon. Until the archs are
      ported over to the new MCOUNT_RECORD method, I am disabling dynamic
      ftrace from them.
      
      Note: I am leaving in the arch/<arch>/kernel/ftrace.c code alone since
      that can be used when the arch is ported to MCOUNT_RECORD. To port
      the arch to MCOUNT_RECORD, the scripts/recordmcount.pl needs to be
      updated. I will make that easier to do for 2.6.29. For 28, we will keep
      the archs disabled.
      Signed-off-by: NSteven Rostedt <srostedt@redhat.com>
      Signed-off-by: NIngo Molnar <mingo@elte.hu>
      07c4cc1c
  14. 22 10月, 2008 1 次提交
    • B
      [ARM] msm: rename ARCH_MSM7X00A to ARCH_MSM · 1637de0c
      Brian Swetland 提交于
      The MSM architecture covers a wider family of chips than just the MSM7X00A.
      Move to a more generic name, in perparation for supporting the specific
      SoC variants as sub-architectures (ARCH_MSM7X01A, ARCH_MSM722X, etc).  This
      gives us ARCH_MSM for the (many) common peripherals.
      
      This also removes the unused/obsolete config item MSM7X00A_IDLE.
      Signed-off-by: NBrian Swetland <swetland@google.com>
      1637de0c
  15. 21 10月, 2008 1 次提交
  16. 20 10月, 2008 1 次提交
    • M
      container freezer: implement freezer cgroup subsystem · dc52ddc0
      Matt Helsley 提交于
      This patch implements a new freezer subsystem in the control groups
      framework.  It provides a way to stop and resume execution of all tasks in
      a cgroup by writing in the cgroup filesystem.
      
      The freezer subsystem in the container filesystem defines a file named
      freezer.state.  Writing "FROZEN" to the state file will freeze all tasks
      in the cgroup.  Subsequently writing "RUNNING" will unfreeze the tasks in
      the cgroup.  Reading will return the current state.
      
      * Examples of usage :
      
         # mkdir /containers/freezer
         # mount -t cgroup -ofreezer freezer  /containers
         # mkdir /containers/0
         # echo $some_pid > /containers/0/tasks
      
      to get status of the freezer subsystem :
      
         # cat /containers/0/freezer.state
         RUNNING
      
      to freeze all tasks in the container :
      
         # echo FROZEN > /containers/0/freezer.state
         # cat /containers/0/freezer.state
         FREEZING
         # cat /containers/0/freezer.state
         FROZEN
      
      to unfreeze all tasks in the container :
      
         # echo RUNNING > /containers/0/freezer.state
         # cat /containers/0/freezer.state
         RUNNING
      
      This is the basic mechanism which should do the right thing for user space
      task in a simple scenario.
      
      It's important to note that freezing can be incomplete.  In that case we
      return EBUSY.  This means that some tasks in the cgroup are busy doing
      something that prevents us from completely freezing the cgroup at this
      time.  After EBUSY, the cgroup will remain partially frozen -- reflected
      by freezer.state reporting "FREEZING" when read.  The state will remain
      "FREEZING" until one of these things happens:
      
      	1) Userspace cancels the freezing operation by writing "RUNNING" to
      		the freezer.state file
      	2) Userspace retries the freezing operation by writing "FROZEN" to
      		the freezer.state file (writing "FREEZING" is not legal
      		and returns EIO)
      	3) The tasks that blocked the cgroup from entering the "FROZEN"
      		state disappear from the cgroup's set of tasks.
      
      [akpm@linux-foundation.org: coding-style fixes]
      [akpm@linux-foundation.org: export thaw_process]
      Signed-off-by: NCedric Le Goater <clg@fr.ibm.com>
      Signed-off-by: NMatt Helsley <matthltc@us.ibm.com>
      Acked-by: NSerge E. Hallyn <serue@us.ibm.com>
      Tested-by: NMatt Helsley <matthltc@us.ibm.com>
      Signed-off-by: NAndrew Morton <akpm@linux-foundation.org>
      Signed-off-by: NLinus Torvalds <torvalds@linux-foundation.org>
      dc52ddc0
  17. 17 10月, 2008 1 次提交
  18. 10 10月, 2008 1 次提交
    • N
      [ARM] 5295/1: make ZONE_DMA optional · 3bca103a
      Nicolas Pitre 提交于
      Most ARM machines don't need a special "DMA" memory zone, and
      when configured out, the kernel becomes a bit smaller:
      
      |   text    data     bss     dec     hex filename
      |3826182  102384  111700 4040266  3da64a vmlinux
      |3823593  101616  111700 4036909  3d992d vmlinux.nodmazone
      
      This is because the system now has only one zone total which effect is
      to optimize away many conditionals in page allocation paths.
      
      So let's configure this zone only on machines that need split zones.
      Signed-off-by: NNicolas Pitre <nico@marvell.com>
      Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
      3bca103a
  19. 02 10月, 2008 5 次提交
  20. 26 9月, 2008 1 次提交
    • L
      [ARM] Orion: add 88F6183 (Orion-1-90) support · d323ade1
      Lennert Buytenhek 提交于
      The Orion-1-90 (88F6183) is another member of the Orion SoC family,
      which has a 16 bit DDR2 interface, one x1 PCIe port (configurable as
      Root Complex or Endpoint), one 10/100/1000 ethernet interface, one
      USB 2.0 port with PHY, one SPDIF/I2S interface, one SDIO interface,
      one TWSI interface, two UARTs, one SPI interface, a NAND controller,
      a crypto engine, and a 4-channel DMA engine.
      Signed-off-by: NLennert Buytenhek <buytenh@marvell.com>
      d323ade1
  21. 17 9月, 2008 2 次提交
  22. 07 9月, 2008 2 次提交
  23. 01 9月, 2008 3 次提交