The nand_chip::erase_cmd callback previously served a dual purpose; for
one, it allowed a per-flash-chip override, so that AG-AND devices could
use a different erase command than other NAND. These AND devices were
dropped in commit 14c65786 (mtd: nand:
remove AG-AND support). On the other hand, some drivers (denali and
doc-g4) need to use this sort of callback to implement
controller-specific erase operations.

To make the latter operation easier for some drivers (e.g., ST's new BCH
NAND driver), it helps if the command dispatch and wait functions can be
lumped together, rather than called separately.

This patch does two things:
 1. Pull the call to chip->waitfunc() into chip->erase_cmd(), and return
    the status from this callback
 2. Rename erase_cmd() to just erase(), since this callback does a
    little more than just send a command
Signed-off-by: NBrian Norris <computersforpeace@gmail.com>
Tested-by: NLee Jones <lee.jones@linaro.org>

Signed-off-by: NMasahiro Yamada <yamada.m@jp.panasonic.com>
Signed-off-by: NBrian Norris <computersforpeace@gmail.com>

More and more chips use the GPMI controller, but these chips may use different
version of the IPs for GPMI and BCH. Different IPs have
 different features, such as the BCH's maximum ECC strength:

     imx23/imx28 -- the BCH's maximum ECC strength is 20
     imx6q       -- the BCH's maximum ECC strength is 40
     imx6sx      -- the BCH's maximum ECC strength is 62

This patch does the following things:

  [1] add a new data structure, gpmi_devdata{}, to store the information for
      each IP. Besides the IP version, we store the following information:
         <1> BCH's maximum ECC strength.
         <2> the maximum chain delay in ns used by the EDO mode.

      but we may add more information in future.

  [2] add the gpmi_devdata_imx{23|28|6q} to replace the gpmi_ids.

  [3] simplify the code by using the ECC strength from gpmi_devdata, such as
      gpmi_check_ecc() and legacy_set_geometry();

  [4] use the maximum chain delay to initialize the EDO mode,
      see gpmi_compute_edo_timing().

  [5] rewrite the macros, such GPMI_IS_MX{23|28|6Q}.
Signed-off-by: NHuang Shijie <b32955@freescale.com>
Signed-off-by: NBrian Norris <computersforpeace@gmail.com>

Add line feed to pr_err.
Signed-off-by: NRaphaël Poggi <poggi.raph@gmail.com>
Signed-off-by: NBrian Norris <computersforpeace@gmail.com>

Sub page write doesn't work because of hw issue in controller found on
Keystone SOCs. AEMIF controller is also used on DaVinci SOCs which
don't seems to have any issue. So add "ti,keysone-nand" compatible
to nand driver in order to set NAND_NO_SUBPAGE_WRITE option.

Cc: Warner Losh <imp@bsdimp.com>
Signed-off-by: NMurali Karicheri <m-karicheri2@ti.com>
Signed-off-by: NIvan Khoronzhuk <ivan.khoronzhuk@ti.com>
Acked-by: NSantosh Shilimkar <santosh.shilimkar@ti.com>
Signed-off-by: NBrian Norris <computersforpeace@gmail.com>

Now that the index variable is correctly set earlier in this function
we can use it in other places that compute the same thing too.
Signed-off-by: NRon Lee <ron@debian.org>
Signed-off-by: NBrian Norris <computersforpeace@gmail.com>

Commit 2c9f2365 (mtd: nand: omap: ecc.calculate: merge omap3_calculate_ecc_bch4
in omap_calculate_ecc_bch) introduced minor compile warning
"‘erased_sector_bitflips’ defined but not used [-Wunused-function]" when
compiling without CONFIG_MTD_NAND_OMAP_BCH. Move function
erased_sector_bitflips() into the same ifdef section as the only caller.
Signed-off-by: NChristian Engelmayer <cengelma@gmx.at>
Reviewed-by: NJingoo Han <jg1.han@samsung.com>
Acked-by: NPekon Gupta <pekon@ti.com>
Signed-off-by: NBrian Norris <computersforpeace@gmail.com>

Commit 7351d3a5 added an index variable
as part of fixing checkpatch warnings, presumably as a tool to make some
long lines shorter, however it only set that index in the case of there
being no gaps in eccpos for the fragment being read.  Which means the
later step of filling ecccode from oob_poi will use the wrong indexing
into eccpos in that case.

This patch restores the behaviour that existed prior to that change.
Signed-off-by: NRon Lee <ron@debian.org>
Signed-off-by: NBrian Norris <computersforpeace@gmail.com>

Passing a name to request_mem_region() isn't optional and can't just
be NULL. Passing NULL causes a NULL ptr deref later in the boot
process.
Signed-off-by: NSasha Levin <sasha.levin@oracle.com>
Tested-by: NAlexander Shiyan <shc_work@mail.ru>
Cc: <stable@vger.kernel.org> # 3.14
Signed-off-by: NBrian Norris <computersforpeace@gmail.com>

Mention to CONFIG_MTD_ECC_BCH in the warning message can be confusing as this
doesn't match the exact name of the configuration option.
This warning showed up once to me when I was starting to set up BCH. After
checking my .config file, it took a moment before realizing it is
CONFIG_MTD_NAND_ECC_BCH instead of CONFIG_MTD_ECC_BCH.
Signed-off-by: NErico Nunes <nunes.erico@gmail.com>
Acked-by: NLee Jones <lee.jones@linaro.org>
Signed-off-by: NBrian Norris <computersforpeace@gmail.com>

Use devm_ioremap_resource() in order to make the code simpler,
and remove redundant return value check of platform_get_resource()
because the value is checked by devm_ioremap_resource(). Also,
'unsigned long mem_size' is removed from 'struct omap_nand_info',
because the 'mem_size' variable is not necessary anymore.
Signed-off-by: NJingoo Han <jg1.han@samsung.com>
Signed-off-by: NBrian Norris <computersforpeace@gmail.com>

Use devm_ioremap_resource() in order to make the code
simpler, and remove redundant return value check of
platform_get_resource_byname() because the value is
checked by devm_ioremap_resource().
Signed-off-by: NJingoo Han <jg1.han@samsung.com>
Tested-by: NDinh Nguyen <dinguyen@altera.com>
Signed-off-by: NBrian Norris <computersforpeace@gmail.com>

ELM hardware engine is used by BCH ecc-schemes for detecting and locating ECC
errors. This patch adds the following checks for ELM hardware engine:

 - ELM internal buffers are of 1K,
   so it cannot process data with ecc-step-size > 1K.

 - ELM engine can execute upto maximum of 8 threads in parallel,
   so in *page-mode* (when complete page is processed in single iteration),
   ELM cannot support ecc-steps > 8.
Signed-off-by: NPekon Gupta <pekon@ti.com>
Reviewed-by: NEzequiel Garcia <ezequiel.garcia@free-electrons.com>
Signed-off-by: NBrian Norris <computersforpeace@gmail.com>

'is_elm_present' flag is not used anywhere. This check is implicitely
taken care while selecting appropriate ecc-scheme via DT or board-file.
Signed-off-by: NPekon Gupta <pekon@ti.com>
Signed-off-by: NBrian Norris <computersforpeace@gmail.com>

This patch
 - refactors GPMC configurations based on ecc-scheme
 - removed dependency on is_elm_present() flag, which is implicitely
   taken care by selecting appropriate ecc-scheme
Signed-off-by: NPekon Gupta <pekon@ti.com>
Signed-off-by: NBrian Norris <computersforpeace@gmail.com>

Lots of if..then..else conditions in omap_enable_hwecc_bch() can be avoided if
code is refactored based on ecc-scheme.
Signed-off-by: NPekon Gupta <pekon@ti.com>
Signed-off-by: NBrian Norris <computersforpeace@gmail.com>

This patch
 - renames omap3_enable_hwecc_bch -> omap_enable_hwecc_bch to keep
   nomenclature independent of any device family.
 - using '__maybe_unused' instead of `ifdef based conditional compilation
   to suppress warning for un-used functions
Signed-off-by: NPekon Gupta <pekon@ti.com>
Signed-off-by: NBrian Norris <computersforpeace@gmail.com>

merge omap3_calculate_ecc_bch8() into omap_calculate_ecc_bch() so that
common callback can be used for both OMAP_ECC_BCH8_CODE_HW and
OMAP_ECC_BCH8_CODE_HW_DETECTION_SW
+---------------------+-------------------------------------------------------+
|ecc-scheme           | nand_chip->calculate() after this patch               |
+---------------------+-------------------------------------------------------+
|HAM1_ECC             | omap_calculate_ecc()                                  |
+---------------------+-------------------------------------------------------+
|BCH4_HW_DETECTION_SW | omap_calculate_ecc_bch()                              |
|BCH4_HW              | omap_calculate_ecc_bch()                              |
|BCH8_HW_DETECTION_SW | omap3_calculate_ecc_bch8() -> omap_calculate_ecc_bch()|
|BCH8_HW              | omap_calculate_ecc_bch()                              |
+---------------------+-------------------------------------------------------+
Tested-by: NStefan Roese <sr@denx.de>
Signed-off-by: NPekon Gupta <pekon@ti.com>
Signed-off-by: NBrian Norris <computersforpeace@gmail.com>

merges omap3_calculate_ecc_bch4() into omap_calculate_ecc_bch() so that
common callback can be used for both OMAP_ECC_BCH4_CODE_HW and
OMAP_ECC_BCH4_CODE_HW_DETECTION_SW ecc-schemes

+---------------------+-------------------------------------------------------+
|ecc-scheme           | nand_chip->calculate() after this patch               |
+---------------------+-------------------------------------------------------+
|HAM1_ECC             | omap_calculate_ecc()                                  |
+---------------------+-------------------------------------------------------+
|BCH4_HW_DETECTION_SW | omap3_calculate_ecc_bch4() -> omap_calculate_ecc_bch()|
|BCH4_HW              | omap_calculate_ecc_bch()                              |
|BCH8_HW_DETECTION_SW | omap3_calculate_ecc_bch8()                            |
|BCH8_HW              | omap_calculate_ecc_bch()                              |
+---------------------+-------------------------------------------------------+
Tested-by: NStefan Roese <sr@denx.de>
Signed-off-by: NPekon Gupta <pekon@ti.com>
Signed-off-by: NBrian Norris <computersforpeace@gmail.com>

OMAP NAND driver supports multiple flavours of BCH4 and BCH8 ECC algorithms.
+------+------------------------------------+---------------+---------------+
| Algo | ECC scheme                         |ECC calculation|Error detection|
+------+------------------------------------+---------------+---------------+
|      |OMAP_ECC_BCH4_CODE_HW_DETECTION_SW  |H/W (GPMC)     |S/W            |
| BCH4 |OMAP_ECC_BCH4_CODE_HW               |H/W (GPMC)     |H/W (ELM)      |
+------+------------------------------------+---------------+---------------+
|      |OMAP_ECC_BCH8_CODE_HW_DETECTION_SW  |H/W (GPMC)     |S/W            |
| BCH8 |OMAP_ECC_BCH8_CODE_HW               |H/W (GPMC)     |H/W (ELM)      |
+------+------------------------------------+---------------+---------------+

This patch refactors omap_calculate_ecc_bch() so that
 - separate out ecc-scheme specific code so that common-code can be reused
   between different implementations of same ECC algorithm.
 - new ecc-schemes can be added with ease in future.
Tested-by: NStefan Roese <sr@denx.de>
Signed-off-by: NPekon Gupta <pekon@ti.com>
Signed-off-by: NBrian Norris <computersforpeace@gmail.com>

rename omap3_calculate_ecc_bch -> omap_calculate_ecc_bch to
keep nomenclature independent of any device family.
Tested-by: NStefan Roese <sr@denx.de>
Signed-off-by: NPekon Gupta <pekon@ti.com>
Signed-off-by: NBrian Norris <computersforpeace@gmail.com>

This patch updates following checks when bit-flips are detected by ELM:

 - Do not evaluate bit-flips when un-correctable bit-flips is reported by ELM,
   because as per [1] when ELM reports an un-correctable bit-flips,
   'number of error' field in its ELM_LOCATION_STATUS register is also invalid.

 - Return with error-code '-EBADMSG' on detection of un-correctable bit-flip.

 - Return with error-code '-EBADMSG' when bit-flips position is outside current
   Sector and OOB area.

[1] ELM IP spec Table-25 ELM_LOCATION_STATUS Register.
    ELM_LOCATION_STATUS[8] = ECC_CORRECTABLE: Error location process exit status
        0x0: ECC error location process failed.
             Number of errors and error locations are invalid.
        0x1: all errors were successfully located.
             Number of errors and error locations are valid.
Tested-by: NStefan Roese <sr@denx.de>
Signed-off-by: NPekon Gupta <pekon@ti.com>
Signed-off-by: NBrian Norris <computersforpeace@gmail.com>

Current omap_elm_correct_data() code is not scalable for future ecc-schemes
due to presence of tweaks and hard-coded macros for BCH4_ECC and BCH8_ECC
ecc-schemes at multiple places.

This patch:
 - replaces 'ecc_opt' with '(info->nand.ecc.strength == BCH8_MAX_ERROR)
   used to differentiate between BCH8_HW and BCH4_SW
 - replaces macros (defining magic number for specific ecc-scheme) with
   generic variables
 - removes dependency on macros defined in elm.h (like BCHx_ECC_OOB_BYTES)
Tested-by: NStefan Roese <sr@denx.de>
Signed-off-by: NPekon Gupta <pekon@ti.com>
Signed-off-by: NBrian Norris <computersforpeace@gmail.com>

mtd: nand: omap: ecc.correct: omap_elm_correct_data: fix erased-page detection for BCHx_HW ECC schemes

As erased-pages do not have ECC stored in their OOB area, so they need to be
seperated out from programmed-pages, before doing BCH ECC correction.

In current implementation of omap_elm_correct_data() which does ECC correction
for BCHx ECC schemes, this erased-pages are detected based on specific marker
byte (reserved as 0x00) in ecc-layout.
However, this approach has some limitation like;
 1) All ecc-scheme layouts do not have such Reserved byte marker to
    differentiate between erased-page v/s programmed-page. Thus this is a
    customized solution.
 2) Reserved marker byte can itself be subjected to bit-flips causing
    erased-page to be misunderstood as programmed-page.

This patch removes dependency on any marker byte in ecc-layout, instead it
compares calc_ecc[] with pattern of ECC-of-all(0xff). This implicitely
means that both 'data + oob == all(0xff).
Signed-off-by: NPekon Gupta <pekon@ti.com>
Signed-off-by: NBrian Norris <computersforpeace@gmail.com>

mtd: nand: omap: ecc.correct: omap_elm_correct_data: rename ambiguous variable 'eccsize' and 'ecc_vector_size'

renaming following variables as they cause confusion due to resemblence to
another similar field in 'struct nand_ecc_ctrl' (nand_chip->ecc.size).
renaming: ecc_vector_size --> ecc->bytes	(info->nand.ecc.bytes)
renaming: eccsize         --> actual_eccbytes	(info->nand.ecc.bytes - 1) for BCH4 and BCH8
Tested-by: NStefan Roese <sr@denx.de>
Signed-off-by: NPekon Gupta <pekon@ti.com>
Signed-off-by: NBrian Norris <computersforpeace@gmail.com>

Information of currently selected ECC scheme 'enum omap_ecc ecc_opt' should
available outside platform-data, so that single nand_chip->ecc callback can
support multiple ecc-scheme configurations.
Tested-by: NStefan Roese <sr@denx.de>
Signed-off-by: NPekon Gupta <pekon@ti.com>
Signed-off-by: NBrian Norris <computersforpeace@gmail.com>

Crash detected on sam5d35 and its pmecc nand ecc controller.

The problem was a call to chip->ecc.hwctl from nand_write_subpage_hwecc
(nand_base.c) when we write a sub page.
chip->ecc.hwctl function is not set when we are using PMECC controller.
As a workaround, set NAND_NO_SUBPAGE_WRITE for PMECC controller in
order to disable sub page access in nand_write_page.
Signed-off-by: NHerve Codina <Herve.CODINA@celad.com>
Acked-by: NJosh Wu <josh.wu@atmel.com>
Cc: stable@vger.kernel.org
Signed-off-by: NBrian Norris <computersforpeace@gmail.com>

1) Why add the subpage read support?
  The page size of the nand chip becomes larger and larger, the imx6 has to
  supports the 16K page or even bigger page. But sometimes, the upper layer only
  needs a small part of the page, such as 512 bytes or less.

  For example, ubiattach may only read 64 bytes per page.

2) We only enable the subpage read support when it meets the conditions:
   <1> the chip is imx6 (or later chips) which can supports large nand page.
   <2> the size of ECC parity is byte aligned.
       If the size of ECC parity is not byte aligned, the calling of NAND_CMD_RNDOUT
       will fail.

3) What does this patch do?
   This patch will fake a virtual small page for the subpage read, and call the
   gpmi_ecc_read_page() to do the real work.

   In order to fake a virtual small page, the patch changes the BCH registers and
   the bch_geometry{}. After the subpage read finished, we will restore them back.

4) Performace:
    4.1) Tested with Toshiba TC58NVG2S0F(4096 + 224) with the following command:
         #ubiattach /dev/ubi_ctrl -m 4

       The detail information of /dev/mtd4 shows below:
       --------------------------------------------------------------
       #mtdinfo /dev/mtd4
        mtd4
        Name:                           test
        Type:                           nand
        Eraseblock size:                262144 bytes, 256.0 KiB
        Amount of eraseblocks:          1856 (486539264 bytes, 464.0 MiB)
        Minimum input/output unit size: 4096 bytes
        Sub-page size:                  4096 bytes
        OOB size:                       224 bytes
        Character device major/minor:   90:8
        Bad blocks are allowed:         true
        Device is writable:             true
       --------------------------------------------------------------

    4.2) Before this patch:
       --------------------------------------------------------------
       [   94.530495] UBI: attaching mtd4 to ubi0
       [   98.928850] UBI: scanning is finished
       [   98.953594] UBI: attached mtd4 (name "test", size 464 MiB) to ubi0
       [   98.958562] UBI: PEB size: 262144 bytes (256 KiB), LEB size: 253952 bytes
       [   98.964076] UBI: min./max. I/O unit sizes: 4096/4096, sub-page size 4096
       [   98.969518] UBI: VID header offset: 4096 (aligned 4096), data offset: 8192
       [   98.975128] UBI: good PEBs: 1856, bad PEBs: 0, corrupted PEBs: 0
       [   98.979843] UBI: user volume: 1, internal volumes: 1, max. volumes count: 128
       [   98.985878] UBI: max/mean erase counter: 2/1, WL threshold: 4096, image sequence number: 2024916145
       [   98.993635] UBI: available PEBs: 0, total reserved PEBs: 1856, PEBs reserved for bad PEB handling: 40
       [   99.001807] UBI: background thread "ubi_bgt0d" started, PID 831
       --------------------------------------------------------------
       The attach time is about 98.9 - 94.5 = 4.4s

    4.3) After this patch:
       --------------------------------------------------------------
       [  286.464906] UBI: attaching mtd4 to ubi0
       [  289.186129] UBI: scanning is finished
       [  289.211416] UBI: attached mtd4 (name "test", size 464 MiB) to ubi0
       [  289.216360] UBI: PEB size: 262144 bytes (256 KiB), LEB size: 253952 bytes
       [  289.221858] UBI: min./max. I/O unit sizes: 4096/4096, sub-page size 4096
       [  289.227293] UBI: VID header offset: 4096 (aligned 4096), data offset: 8192
       [  289.232878] UBI: good PEBs: 1856, bad PEBs: 0, corrupted PEBs: 0
       [  289.237628] UBI: user volume: 0, internal volumes: 1, max. volumes count: 128
       [  289.243553] UBI: max/mean erase counter: 1/1, WL threshold: 4096, image sequence number: 2024916145
       [  289.251348] UBI: available PEBs: 1812, total reserved PEBs: 44, PEBs reserved for bad PEB handling: 40
       [  289.259417] UBI: background thread "ubi_bgt0d" started, PID 847
       --------------------------------------------------------------
       The attach time is about 289.18 - 286.46 = 2.7s

     4.4) The conclusion:
       We achieve (4.4 - 2.7) / 4.4 = 38.6% faster in the ubiattach.
Signed-off-by: NHuang Shijie <b32955@freescale.com>
Signed-off-by: NBrian Norris <computersforpeace@gmail.com>

The nfc_geo->payload_size is equal to the mtd->writesize now,
use the nfc_geo->payload_size to replace the mtd->writesize.

This patch makes preparation for the gpmi's subpage read support.
In the subpage support, the nfc_geo->payload_size maybe smaller then
the mtd->writesize.
Signed-off-by: NHuang Shijie <b32955@freescale.com>
Signed-off-by: NBrian Norris <computersforpeace@gmail.com>

Add the "page" argument for the read_subpage hook. With this argument,
the implementation of this hook could prints out more accurate information
for debugging.
Signed-off-by: NHuang Shijie <b32955@freescale.com>
Signed-off-by: NBrian Norris <computersforpeace@gmail.com>

The nand_get_flash_type parameter "busw" input value is not used by any
branch, and it is updated before use it in the function, so remove it,
define the "busw" as an internal variable.
Signed-off-by: NCai Zhiyong <caizhiyong@huawei.com>
Signed-off-by: NBrian Norris <computersforpeace@gmail.com>

The actual ECC strength used to select the ECC scheme is 'ecc_strength'.
Use it in the error message.
Signed-off-by: NEzequiel Garcia <ezequiel.garcia@free-electrons.com>
Signed-off-by: NBrian Norris <computersforpeace@gmail.com>

This macro is not used so it's safe to remove it.
Signed-off-by: NEzequiel Garcia <ezequiel.garcia@free-electrons.com>
Signed-off-by: NBrian Norris <computersforpeace@gmail.com>

Instead of writing to "nand->reg + REG_FMICSR" we write to "REG_FMICSR"
which is NULL and not a valid register.

Fixes: 8bff82cb ('mtd: add nand support for w90p910 (v2)')
Signed-off-by: NDan Carpenter <dan.carpenter@oracle.com>
Signed-off-by: NBrian Norris <computersforpeace@gmail.com>

Check the chip->jedec_version, and print out the right information
for JEDEC compliant NAND.
Signed-off-by: NHuang Shijie <b32955@freescale.com>
Signed-off-by: NBrian Norris <computersforpeace@gmail.com>

This patch adds the parsing code for the JEDEC compliant NAND.

Since we need the 0x40 as the column address, this patch also
makes the NAND_CMD_PARAM to use the 8-bit address only.
Signed-off-by: NHuang Shijie <b32955@freescale.com>
Signed-off-by: NBrian Norris <computersforpeace@gmail.com>

Check the return value from platform_get_irq() and propagate it in the case of
error.
Signed-off-by: NFabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: NBrian Norris <computersforpeace@gmail.com>

PIO fall back is not an issue, so don't make this much noise.
Signed-off-by: NNicolas Ferre <nicolas.ferre@atmel.com>
Signed-off-by: NBrian Norris <computersforpeace@gmail.com>

read_buf is called in place of write_buf in the
nand_write_page_raw_syndrome function.
Signed-off-by: NBoris BREZILLON <b.brezillon.dev@gmail.com>
Signed-off-by: NBrian Norris <computersforpeace@gmail.com>

On archs like S390 or um this driver cannot build nor work.
Make it depend on HAS_IOMEM and HAS_DMA to bypass build failures.

drivers/built-in.o: In function `flctl_probe':
drivers/mtd/nand/sh_flctl.c:1097: undefined reference to `devm_ioremap_resource'
drivers/built-in.o: In function `flctl_dma_fifo0_transfer':
drivers/mtd/nand/sh_flctl.c:368: undefined reference to `dma_map_single'
drivers/mtd/nand/sh_flctl.c:407: undefined reference to `dma_unmap_single'
Signed-off-by: NRichard Weinberger <richard@nod.at>
Signed-off-by: NBrian Norris <computersforpeace@gmail.com>