1. 08 12月, 2011 8 次提交
  2. 31 3月, 2011 1 次提交
  3. 29 3月, 2011 1 次提交
    • D
      MIPS: Octeon: Rewrite interrupt handling code. · 0c326387
      David Daney 提交于
      This includes conversion to new style irq_chip functions, and
      correctly enabling/disabling per-CPU interrupts.
      
      The hardware interrupt bit to irq number mapping is now done with a
      flexible map, instead of by bit twiddling the irq number.
      
      [ tglx: Adjusted to new irq_cpu_on/offline callbacks and
              __irq_set_affinity_lock ]
      Signed-off-by: NDavid Daney <ddaney@caviumnetworks.com>
      Cc: linux-mips@linux-mips.org
      Cc: ralf@linux-mips.org
      LKML-Reference: <1301081931-11240-5-git-send-email-ddaney@caviumnetworks.com>
      Signed-off-by: NThomas Gleixner <tglx@linutronix.de>
      0c326387
  4. 30 10月, 2010 6 次提交
  5. 05 8月, 2010 3 次提交
  6. 27 2月, 2010 2 次提交
  7. 17 12月, 2009 3 次提交
  8. 18 9月, 2009 2 次提交
  9. 03 7月, 2009 1 次提交
  10. 17 6月, 2009 5 次提交
  11. 11 1月, 2009 3 次提交
    • D
      MIPS: Add Cavium OCTEON processor support files to arch/mips/cavium-octeon. · 5b3b1688
      David Daney 提交于
      These are the rest of the new files needed to add OCTEON processor
      support to the Linux kernel.  Other than Makefile and Kconfig which
      should be obvious, we have:
      
      csrc-octeon.c   -- Clock source driver for OCTEON.
      dma-octeon.c    -- Helper functions for mapping DMA memory.
      flash_setup.c   -- Register on-board flash with the MTD subsystem.
      octeon-irq.c    -- OCTEON interrupt controller managment.
      octeon-memcpy.S -- Optimized memcpy() implementation.
      serial.c        -- Register 8250 platform driver and early console.
      setup.c         -- Early architecture initialization.
      smp.c           -- OCTEON SMP support.
      octeon_switch.S -- Scheduler context switch for OCTEON.
      c-octeon.c      -- OCTEON cache controller support.
      cex-oct.S       -- OCTEON cache exception handler.
      
      asm/mach-cavium-octeon/*.h -- Architecture include files.
      Signed-off-by: NTomaso Paoletti <tpaoletti@caviumnetworks.com>
      Signed-off-by: NDavid Daney <ddaney@caviumnetworks.com>
      Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
      
       create mode 100644 arch/mips/cavium-octeon/Kconfig
       create mode 100644 arch/mips/cavium-octeon/Makefile
       create mode 100644 arch/mips/cavium-octeon/csrc-octeon.c
       create mode 100644 arch/mips/cavium-octeon/dma-octeon.c
       create mode 100644 arch/mips/cavium-octeon/flash_setup.c
       create mode 100644 arch/mips/cavium-octeon/octeon-irq.c
       create mode 100644 arch/mips/cavium-octeon/octeon-memcpy.S
       create mode 100644 arch/mips/cavium-octeon/serial.c
       create mode 100644 arch/mips/cavium-octeon/setup.c
       create mode 100644 arch/mips/cavium-octeon/smp.c
       create mode 100644 arch/mips/include/asm/mach-cavium-octeon/cpu-feature-overrides.h
       create mode 100644 arch/mips/include/asm/mach-cavium-octeon/dma-coherence.h
       create mode 100644 arch/mips/include/asm/mach-cavium-octeon/irq.h
       create mode 100644 arch/mips/include/asm/mach-cavium-octeon/kernel-entry-init.h
       create mode 100644 arch/mips/include/asm/mach-cavium-octeon/war.h
       create mode 100644 arch/mips/include/asm/octeon/octeon.h
       create mode 100644 arch/mips/kernel/octeon_switch.S
       create mode 100644 arch/mips/mm/c-octeon.c
       create mode 100644 arch/mips/mm/cex-oct.S
      5b3b1688
    • D
      MIPS: Add Cavium OCTEON processor support files to... · 58f07778
      David Daney 提交于
      MIPS: Add Cavium OCTEON processor support files to arch/mips/cavium-octeon/executive and asm/octeon.
      
      These files are used to coordinate resource sharing between all of
      the programs running on the OCTEON SOC.  The OCTEON processor has many
      CPU cores (current parts have up to 16, but more are possible).  It
      also has a variety of on-chip hardware blocks for things like network
      acceleration, encryption and RAID.
      
      One typical configuration is to run Linux on several of the CPU cores,
      and other dedicated applications on the other cores.
      
      Resource allocation between the various programs running on the system
      (Linux kernel and other dedicated applications) needs to be
      coordinated.  The code we use to do this we call the 'executive'.  All
      of this resource allocation and sharing code is gathered together in
      the executive directory.
      
      Included in the patch set are the following files:
      
      cvmx-bootmem.c and cvmx-sysinfo.c -- Coordinate memory allocation.
      All memory used by the Linux kernel is obtained here at boot time.
      
      cvmx-l2c.c -- Coordinates operations on the shared level 2 cache.
      
      octeon-model.c  -- Probes chip capabilities and version.
      
      The corresponding headers are in asm/octeon.
      Signed-off-by: NTomaso Paoletti <tpaoletti@caviumnetworks.com>
      Signed-off-by: NDavid Daney <ddaney@caviumnetworks.com>
      Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
      
       create mode 100644 arch/mips/cavium-octeon/executive/Makefile
       create mode 100644 arch/mips/cavium-octeon/executive/cvmx-bootmem.c
       create mode 100644 arch/mips/cavium-octeon/executive/cvmx-l2c.c
       create mode 100644 arch/mips/cavium-octeon/executive/cvmx-sysinfo.c
       create mode 100644 arch/mips/cavium-octeon/executive/octeon-model.c
       create mode 100644 arch/mips/include/asm/octeon/cvmx-asm.h
       create mode 100644 arch/mips/include/asm/octeon/cvmx-bootinfo.h
       create mode 100644 arch/mips/include/asm/octeon/cvmx-bootmem.h
       create mode 100644 arch/mips/include/asm/octeon/cvmx-l2c.h
       create mode 100644 arch/mips/include/asm/octeon/cvmx-packet.h
       create mode 100644 arch/mips/include/asm/octeon/cvmx-spinlock.h
       create mode 100644 arch/mips/include/asm/octeon/cvmx-sysinfo.h
       create mode 100644 arch/mips/include/asm/octeon/cvmx.h
       create mode 100644 arch/mips/include/asm/octeon/octeon-feature.h
       create mode 100644 arch/mips/include/asm/octeon/octeon-model.h
      58f07778
    • D
      MIPS: Add Cavium OCTEON processor CSR definitions · 54293ec3
      David Daney 提交于
      Here we define the addresses and bit-fields of the Configuration and
      Status Registers (CSRs) for some of the hardware functional units on
      the OCTEON SOC.
      
      Definitions are needed for:
      
      CIU  -- Central Interrupt Unit.
      GPIO -- General Purpose Input Output.
      IOB  -- Input / Output {Busing,Bridge}.
      IPD  -- Input Packet Data unit.
      L2C  -- Level-2 Cache controller.
      L2D  -- Level-2 Data cache.
      L2T  -- Level-2 cache Tag.
      LED  -- Light Emitting Diode controller.
      MIO  -- Miscellaneous Input / Output.
      POW  -- Packet Order / Work unit.
      Signed-off-by: NTomaso Paoletti <tpaoletti@caviumnetworks.com>
      Signed-off-by: NDavid Daney <ddaney@caviumnetworks.com>
      Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
      54293ec3