1. 08 12月, 2011 3 次提交
  2. 30 10月, 2010 1 次提交
    • K
      MIPS: Decouple BMIPS CPU support from bcm47xx/bcm63xx SoC code · 602977b0
      Kevin Cernekee 提交于
      BMIPS processor cores are used in 50+ different chipsets spread across
      5+ product lines.  In many cases the chipsets do not share the same
      peripheral register layouts, the same register blocks, the same
      interrupt controllers, the same memory maps, or much of anything else.
      
      But, across radically different SoCs that share nothing more than the
      same BMIPS CPU, a few things are still mostly constant:
      
      SMP operations
      Access to performance counters
      DMA cache coherency quirks
      Cache and memory bus configuration
      
      So, it makes sense to treat each BMIPS processor type as a generic
      "building block," rather than tying it to a specific SoC.  This makes it
      easier to support a large number of BMIPS-based chipsets without
      unnecessary duplication of code, and provides the infrastructure needed
      to support BMIPS-proprietary features.
      Signed-off-by: NKevin Cernekee <cernekee@gmail.com>
      Cc: mbizon@freebox.fr
      Cc: linux-mips@linux-mips.org
      Cc: linux-kernel@vger.kernel.org
      Tested-by: NFlorian Fainelli <ffainelli@freebox.fr>
      Patchwork: https://patchwork.linux-mips.org/patch/1706/
      Signed-off-by: Ralf Baechle <ralf@linux-mips.org
      602977b0
  3. 13 4月, 2010 1 次提交
  4. 02 11月, 2009 1 次提交
  5. 18 9月, 2009 1 次提交