1. 26 1月, 2015 1 次提交
  2. 17 7月, 2014 1 次提交
  3. 03 7月, 2014 2 次提交
  4. 12 6月, 2014 1 次提交
    • Y
      net/mlx4_en: Use affinity hint · 9e311e77
      Yuval Atias 提交于
      The “affinity hint” mechanism is used by the user space
      daemon, irqbalancer, to indicate a preferred CPU mask for irqs.
      Irqbalancer can use this hint to balance the irqs between the
      cpus indicated by the mask.
      
      We wish the HCA to preferentially map the IRQs it uses to numa cores
      close to it.  To accomplish this, we use cpumask_set_cpu_local_first(), that
      sets the affinity hint according the following policy:
      First it maps IRQs to “close” numa cores.  If these are exhausted, the
      remaining IRQs are mapped to “far” numa cores.
      Signed-off-by: NYuval Atias <yuvala@mellanox.com>
      Signed-off-by: NAmir Vadai <amirv@mellanox.com>
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      9e311e77
  5. 02 6月, 2014 2 次提交
  6. 09 5月, 2014 1 次提交
  7. 17 4月, 2014 1 次提交
  8. 20 12月, 2013 1 次提交
  9. 08 11月, 2013 2 次提交
  10. 20 6月, 2013 1 次提交
  11. 25 4月, 2013 1 次提交
    • A
      net/mlx4_en: Add HW timestamping (TS) support · ec693d47
      Amir Vadai 提交于
      The patch allows to enable/disable HW timestamping for incoming and/or
      outgoing packets. It adds and initializes all structs and callbacks
      needed by kernel TS API.
      To enable/disable HW timestamping appropriate ioctl should be used.
      Currently HWTSTAMP_FILTER_ALL/NONE and HWTSAMP_TX_ON/OFF only are
      supported.
      When enabling TS on receive flow - VLAN stripping will be disabled.
      Also were made all relevant changes in RX/TX flows to consider TS request
      and plant HW timestamps into relevant structures.
      mlx4_ib was fixed to compile with new mlx4_cq_alloc() signature.
      Signed-off-by: NEugenia Emantayev <eugenia@mellanox.com>
      Signed-off-by: NAmir Vadai <amirv@mellanox.com>
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      ec693d47
  12. 27 11月, 2012 1 次提交
    • O
      mlx4: 64-byte CQE/EQE support · 08ff3235
      Or Gerlitz 提交于
      ConnectX-3 devices can use either 64- or 32-byte completion queue
      entries (CQEs) and event queue entries (EQEs).  Using 64-byte
      EQEs/CQEs performs better because each entry is aligned to a complete
      cacheline.  This patch queries the HCA's capabilities, and if it
      supports 64-byte CQEs and EQES the driver will configure the HW to
      work in 64-byte mode.
      
      The 32-byte vs 64-byte mode is global per HCA and not per CQ or EQ.
      
      Since this mode is global, userspace (libmlx4) must be updated to work
      with the configured CQE size, and guests using SR-IOV virtual
      functions need to know both EQE and CQE size.
      
      In case one of the 64-byte CQE/EQE capabilities is activated, the
      patch makes sure that older guest drivers that use the QUERY_DEV_FUNC
      command (e.g as done in mlx4_core of Linux 3.3..3.6) will notice that
      they need an update to be able to work with the PPF. This is done by
      changing the returned pf_context_behaviour not to be zero any more. In
      case none of these capabilities is activated that value remains zero
      and older guest drivers can run OK.
      
      The SRIOV related flow is as follows
      
      1. the PPF does the detection of the new capabilities using
         QUERY_DEV_CAP command.
      
      2. the PPF activates the new capabilities using INIT_HCA.
      
      3. the VF detects if the PPF activated the capabilities using
         QUERY_HCA, and if this is the case activates them for itself too.
      
      Note that the VF detects that it must be aware to the new PF behaviour
      using QUERY_FUNC_CAP.  Steps 1 and 2 apply also for native mode.
      
      User space notification is done through a new field introduced in
      struct mlx4_ib_ucontext which holds device capabilities for which user
      space must take action. This changes the binary interface so the ABI
      towards libmlx4 exposed through uverbs is bumped from 3 to 4 but only
      when **needed** i.e. only when the driver does use 64-byte CQEs or
      future device capabilities which must be in sync by user space. This
      practice allows to work with unmodified libmlx4 on older devices (e.g
      A0, B0) which don't support 64-byte CQEs.
      
      In order to keep existing systems functional when they update to a
      newer kernel that contains these changes in VF and userspace ABI, a
      module parameter enable_64b_cqe_eqe must be set to enable 64-byte
      mode; the default is currently false.
      Signed-off-by: NEli Cohen <eli@mellanox.com>
      Signed-off-by: NOr Gerlitz <ogerlitz@mellanox.com>
      Signed-off-by: NRoland Dreier <roland@purestorage.com>
      08ff3235
  13. 19 7月, 2012 2 次提交
  14. 24 4月, 2012 1 次提交
  15. 31 12月, 2011 1 次提交
  16. 28 11月, 2011 1 次提交
  17. 10 10月, 2011 2 次提交
  18. 11 8月, 2011 1 次提交
  19. 24 3月, 2011 1 次提交
  20. 25 5月, 2009 1 次提交
  21. 18 5月, 2009 1 次提交
  22. 26 12月, 2008 2 次提交
  23. 22 12月, 2008 1 次提交
  24. 23 10月, 2008 1 次提交