For systems which do not define PHYS_OFFSET as 0 pfn_valid() may falsely
have returned 0 on most configurations.  Bug introduced by commit
752fbeb2e3555c0d236e992f1195fd7ce30e728d (linux-mips.org) rsp.
6f284a2c (kernel.org) titled "[MIPS]
FLATMEM: introduce PHYS_OFFSET."
Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

Move the cavium PCI files to the arch/mips/pci directory.  Also cleanup
comment formatting and code layout.  Code from pci-common.c, was moved
into other files.
Signed-off-by: NDavid Daney <ddaney@caviumnetworks.com>
Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

Signed-off-by: NYoichi Yuasa <yuasa@linux-mips.org>
Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

If an o32 process generates a core dump on a 64 bit kernel, the core file
will not be correctly recognized. This is because ELF_CORE_COPY_REGS and
ELF_CORE_COPY_TASK_REGS are not correctly defined for o32 and will use
the default register set which would be CONFIG_64BIT in asm/elf.h.

So we'll switch to use the right register defines in this situation by
checking for WANT_COMPAT_REG_H and use the right defines of
ELF_CORE_COPY_REGS and ELF_CORE_COPY_TASK_REGS.

[Ralf: made ELF_CORE_COPY_TASK_REGS() bullet-proof against funny arguments.]
Signed-off-by: NYong Zhang <yong.zhang@windriver.com>
Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

This is to move the gcmp_probe call to before the use of and selection of
the smp_ops functions. This allows malta with 1004K to work.
Signed-off-by: NTim Anderson <tanderson@mvista.com>
Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

Most of the CMP support was added before, this mostly correct compile
problems but adds a platform specific translation for the interrupt number
based on cpu number.
Signed-off-by: NTim Anderson <tanderson@mvista.com>
Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

This patch extends the GIC interrupt handling beyond the current 32 bit
range as well as extending the number of interrupts based on the number
of CPUs.
Signed-off-by: NTim Anderson <tanderson@mvista.com>
Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

Some CPUs implement mipsr2, but because they are a super-set of mips64r2 do
not define CONFIG_CPU_MIPS64_R2.  Cavium OCTEON falls into this category.
We would still like to use the optimized implementation, so since we have
already checked for CONFIG_CPU_MIPSR2, checking for CONFIG_64BIT instead of
CONFIG_CPU_MIPS64_R2 is sufficient.
Signed-off-by: NDavid Daney <ddaney@caviumnetworks.com>
Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

Signed-off-by: NYoichi Yuasa <yyuasa@linux.com>
Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

[Ralf: I fixed up the numbering in the comment in scall64-n32.S.]
Signed-off-by: NDavid Daney <ddaney@caviumnetworks.com>
Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

This patch adds support for the Texas Instruments AR7 System-on-a-Chip.
It supports the TNETD7100, 7200 and 7300 versions of the SoC.
Signed-off-by: NMatteo Croce <matteo@openwrt.org>
Signed-off-by: NFelix Fietkau <nbd@openwrt.org>
Signed-off-by: NEugene Konev <ejka@openwrt.org>
Signed-off-by: NNicolas Thill <nico@openwrt.org>
Signed-off-by: NFlorian Fainelli <florian@openwrt.org>
Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

Thanks to Cavium Inc. for the code contribution and help.
Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

Each platform has to add support for CPU hotplugging itself by providing
suitable definitions for the cpu_disable and cpu_die of the smp_ops
methods and setting SYS_SUPPORTS_HOTPLUG_CPU.  A platform should only set
SYS_SUPPORTS_HOTPLUG_CPU once all it's smp_ops definitions have the
necessary changes.  This patch contains the changes to the dummy smp_ops
definition for uni-processor systems.

Parts of the code contributed by Cavium Inc.
Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

Some of the were relying into smp.h being dragged in by another header
which of course is fragile.  <asm/cpu-info.h> uses smp_processor_id()
only in macros and including smp.h there leads to an include loop, so
don't change cpu-info.h.
Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

In the past this file somehow used to be dragged in.
Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

This function was only used by pci_claim_resource(), and the last commit
deleted that use.
Signed-off-by: NMatthew Wilcox <willy@linux.intel.com>
Signed-off-by: NLinus Torvalds <torvalds@linux-foundation.org>

[Ralf: SMP support requires CPU hotplugging which MIPS currently doesn't
support.  As implemented in this patch cache and tlb flushing will also be
invoked with interrupts disabled so smp_call_function() will blow up in
charming ways.  So limit to !SMP.]
Reviewed-by: NPavel Machek <pavel@ucw.cz>
Reviewed-by: NYan Hua <yanh@lemote.com>
Reviewed-by: NArnaud Patard <apatard@mandriva.com>
Reviewed-by: NAtsushi Nemoto <anemo@mba.ocn.ne.jp>
Signed-off-by: NWu Zhangjin <wuzj@lemote.com>
Signed-off-by: NHu Hongbing <huhb@lemote.com>
Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

We had an ugly #ifdef for Cavium Octeon hwrena bits in traps.c, remove
it to mach-cavium-octeon/cpu-feature-overrides.h
Signed-off-by: NDavid Daney <ddaney@caviumnetworks.com>
Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

Some CPUs have implementation dependent rdhwr registers.  Allow them
to be enabled on a per CPU basis.
Signed-off-by: NDavid Daney <ddaney@caviumnetworks.com>
Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

Signed-off-by: NDavid Daney <ddaney@caviumnetworks.com>
Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

Signed-off-by: NDavid Daney <ddaney@caviumnetworks.com>
Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

The octeon-ethernet driver needs to check for additional chip specific
features, we add them to the octeon_has_feature() framework.
Signed-off-by: NDavid Daney <ddaney@caviumnetworks.com>
Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

The bootloader now uses additional board type constants.  The
octeon-ethernet driver needs some of the new values.
Signed-off-by: NDavid Daney <ddaney@caviumnetworks.com>
Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

The various Octeon ethernet drivers use these new functions.
Signed-off-by: NDavid Daney <ddaney@caviumnetworks.com>
Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

The current in-kernel Alchemy GPIO support is far too inflexible for
all my use cases.  To address this, the following changes are made:

* create generic functions which deal with manipulating the on-chip
  GPIO1/2 blocks.  Such functions are universally useful.
* Macros for GPIO2 shared interrupt management and block control.
* support for both built-in CONFIG_GPIOLIB and fast, inlined GPIO macros.

  If CONFIG_GPIOLIB is not enabled, provide linux gpio framework
  compatibility by directly inlining the GPIO1/2 functions.  GPIO access
  is limited to on-chip ones and they can be accessed as documented in
  the datasheets (GPIO0-31 and 200-215).

  If CONFIG_GPIOLIB is selected, two (2) gpio_chip-s, one for GPIO1 and
  one for GPIO2, are registered.  GPIOs can still be accessed by using
  the numberspace established in the databooks.

  However this is not yet flexible enough for my uses:  My Alchemy
  systems have a documented "external" gpio interface (fixed, different
  numberspace) and can support a variety of baseboards, some of which
  are equipped with I2C gpio expanders.  I want to be able to provide
  the default 16 GPIOs of the CPU board numbered as 0..15 and also
  support gpio expanders, if present, starting as gpio16.

  To achieve this, a new Kconfig symbol for Alchemy is introduced,
  CONFIG_ALCHEMY_GPIO_INDIRECT, which boards can enable to signal
  that they don't want the Alchemy numberspace exposed to the outside
  world, but instead want to provide their own.  Boards are now respon-
  sible for providing the linux gpio interface glue code (either in a
  custom gpio.h header (in board include directory) or with gpio_chips).

  To make the board-specific inlined gpio functions work, the MIPS
  Makefile must be changed so that the mach-au1x00/gpio.h header is
  included _after_ the board headers, by moving the inclusion of
  the mach-au1x00/ to the end of the header list.

  See arch/mips/include/asm/mach-au1x00/gpio.h for more info.
Signed-off-by: NManuel Lauss <manuel.lauss@gmail.com>
Acked-by: NFlorian Fainelli <florian@openwrt.org>
Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

Signed-off-by: NManuel Lauss <manuel.lauss@gmail.com>
Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

gpio_direction_output should also set an output value according to the API.

Signed-off-by: Matthieu CASTET <castet.matthieu@free.fr> 
Acked-by: NAurelien Jarno <aurelien@aurel32.net>
Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

 o Rewrite to use <asm-generic/ioctl.h>.  Cuts down the file from 40 to
   16 lines.
 o Delete _IOC_VOID, _IOC_OUT, _IOC_IN and _IOC_INOUT.  They were added
   for 2.1.14 but I was not able to find any user - not even historical
   ones.
Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

Add platform support for RNG of TX4939 SoC.
Signed-off-by: NAtsushi Nemoto <anemo@mba.ocn.ne.jp>
Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

Add a sysdev to access SRAM in TXx9 SoCs via sysfs.
Signed-off-by: NAtsushi Nemoto <anemo@mba.ocn.ne.jp>
Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

Remove commented out definitions.
Signed-off-by: NFlorian Fainelli <florian@openwrt.org>
Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

The Octeon has no execution hazards, so we can remove them and save an
instruction per TLB handler invocation.
Signed-off-by: NDavid Daney <ddaney@caviumnetworks.com>
Reviewed by: David VomLehn <dvomlehn@cisco.com>
Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

Some CPUs do not need ehb instructions after writing CP0 registers.
By allowing ehb generation to be overridden in
cpu-feature-overrides.h, we can save a few instructions in the TLB
handler hot paths.
Signed-off-by: NDavid Daney <ddaney@caviumnetworks.com>
Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

Add platform support for ACLC of TXx9 SoCs.
Signed-off-by: NAtsushi Nemoto <anemo@mba.ocn.ne.jp>
Acked-by: NMark Brown <broonie@opensource.wolfsonmicro.com>
Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

This patch adds support for PCI and PCIe to the base Cavium OCTEON
processor support.
Signed-off-by: NDavid Daney <ddaney@caviumnetworks.com>
Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

Here we add the register definitions for the processor blocks used by
the following PCI support patch.
Signed-off-by: NDavid Daney <ddaney@caviumnetworks.com>
Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

Add platform support for DMAC of TXx9 SoCs.
Signed-off-by: NAtsushi Nemoto <anemo@mba.ocn.ne.jp>
Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

This patch adds support for the integrated DMAC of the TXx9 family.
Signed-off-by: NAtsushi Nemoto <anemo@mba.ocn.ne.jp>
Acked-by: NDan Williams <dan.j.williams@intel.com>
Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

Signed-off-by: NKevin Cernekee <cernekee@gmail.com>
Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

Signed-off-by: NKevin Cernekee <cernekee@gmail.com>
Signed-off-by: NRalf Baechle <ralf@linux-mips.org>