1. 13 12月, 2006 6 次提交
  2. 12 12月, 2006 1 次提交
  3. 10 12月, 2006 1 次提交
  4. 09 12月, 2006 2 次提交
  5. 08 12月, 2006 23 次提交
  6. 06 12月, 2006 1 次提交
  7. 04 12月, 2006 2 次提交
    • A
      [ARM] 3972/1: AT91: Update board.h · c019d49b
      Andrew Victor 提交于
      Replace the 'is_b' variable with 'slot_b' in at91_mmc_data.
      Also add the new 'chipselect' variable for CF/PCMCIA and 'bus_width_16'
      variable for NAND.
      
      This (and previous patches) will unfortunately break the current MMC,
      USB Gadget and PCMCIA drivers.  Updates and fixes for those drivers will
      be submitted to the various subsystem maintainers.
      Signed-off-by: NAndrew Victor <andrew@sanpeople.com>
      Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
      c019d49b
    • L
      [ARM] 3881/4: xscale: clean up cp0/cp1 handling · afe4b25e
      Lennert Buytenhek 提交于
      XScale cores either have a DSP coprocessor (which contains a single
      40 bit accumulator register), or an iWMMXt coprocessor (which contains
      eight 64 bit registers.)
      
      Because of the small amount of state in the DSP coprocessor, access to
      the DSP coprocessor (CP0) is always enabled, and DSP context switching
      is done unconditionally on every task switch.  Access to the iWMMXt
      coprocessor (CP0/CP1) is enabled only when an iWMMXt instruction is
      first issued, and iWMMXt context switching is done lazily.
      
      CONFIG_IWMMXT is supposed to mean 'the cpu we will be running on will
      have iWMMXt support', but boards are supposed to select this config
      symbol by hand, and at least one pxa27x board doesn't get this right,
      so on that board, proc-xscale.S will incorrectly assume that we have a
      DSP coprocessor, enable CP0 on boot, and we will then only save the
      first iWMMXt register (wR0) on context switches, which is Bad.
      
      This patch redefines CONFIG_IWMMXT as 'the cpu we will be running on
      might have iWMMXt support, and we will enable iWMMXt context switching
      if it does.'  This means that with this patch, running a CONFIG_IWMMXT=n
      kernel on an iWMMXt-capable CPU will no longer potentially corrupt iWMMXt
      state over context switches, and running a CONFIG_IWMMXT=y kernel on a
      non-iWMMXt capable CPU will still do DSP context save/restore.
      
      These changes should make iWMMXt work on PXA3xx, and as a side effect,
      enable proper acc0 save/restore on non-iWMMXt capable xsc3 cores such
      as IOP13xx and IXP23xx (which will not have CONFIG_CPU_XSCALE defined),
      as well as setting and using HWCAP_IWMMXT properly.
      Signed-off-by: NLennert Buytenhek <buytenh@wantstofly.org>
      Acked-by: NDan Williams <dan.j.williams@intel.com>
      Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
      afe4b25e
  8. 02 12月, 2006 4 次提交