1. 21 11月, 2018 1 次提交
  2. 21 8月, 2018 1 次提交
  3. 11 12月, 2017 1 次提交
    • M
      xtensa: build kernel with text-section-literals · f8f02ca7
      Max Filippov 提交于
      vmlinux.lds.S doesn't do anything special with literals, so instead of
      keeping them separate put them into the corresponding text sections.
      Drop explicit .literal sections from the vmlinux.lds.S, use standard
      section macros. Mark literal pool locations in the assembly sources.
      Unfortunately assembler doesn't put literals into .init sections and
      external libgcc may still have .literal sections, so sed transformation
      to the linker script is still needed.
      Signed-off-by: NMax Filippov <jcmvbkbc@gmail.com>
      f8f02ca7
  4. 06 6月, 2017 1 次提交
  5. 02 3月, 2017 1 次提交
    • M
      xtensa: allow merging vectors into .text section · b46dcfa3
      Max Filippov 提交于
      Currently code for exception/IRQ vectors is stored in kernel image as
      initialization data and is copied to its working addresses during
      startup. It doesn't always make sense. In many cases vectors location
      can be automatically decided at kernel link time and code can be placed
      right there. This is especially useful for XIP kernel.
      Signed-off-by: NMax Filippov <jcmvbkbc@gmail.com>
      b46dcfa3
  6. 08 10月, 2016 1 次提交
  7. 24 7月, 2016 1 次提交
    • M
      xtensa: cleanup MMU setup and kernel layout macros · a9f2fc62
      Max Filippov 提交于
      Make kernel load address explicit, independent of the selected MMU
      configuration and configurable from Kconfig. Do not restrict it to the
      first 512MB of the physical address space.
      
      Cleanup kernel memory layout macros:
      
      - rename VECBASE_RESET_VADDR to VECBASE_VADDR, XC_VADDR to VECTOR_VADDR;
      - drop VIRTUAL_MEMORY_ADDRESS and LOAD_MEMORY_ADDRESS;
      - introduce PHYS_OFFSET and use it in __va and __pa definitions;
      - synchronize MMU/noMMU vectors, drop unused NMI vector;
      - replace hardcoded vectors offset of 0x3000 with Kconfig symbol.
      Signed-off-by: NMax Filippov <jcmvbkbc@gmail.com>
      a9f2fc62
  8. 03 11月, 2015 2 次提交
    • M
      xtensa: drop unused sections and remapped reset handlers · 0d848afe
      Max Filippov 提交于
      There are no .bootstrap or .ResetVector.text sections linked to the
      vmlinux image, drop these sections from vmlinux.ld.S. Drop
      RESET_VECTOR_VADDR definition only used for .ResetVector.text.
      
      Drop remapped copies of primary and secondary reset vectors, as modern
      gdb don't have problems stepping through instructions at arbitrary
      locations. Drop corresponding sections from the corresponding linker
      scripts.
      Signed-off-by: NMax Filippov <jcmvbkbc@gmail.com>
      0d848afe
    • M
      xtensa: fix secondary core boot in SMP · ab45fb14
      Max Filippov 提交于
      There are multiple factors adding to the issue in different
      configurations:
      
      - commit 17290231 ("xtensa: add fixup for double exception raised
        in window overflow") added function window_overflow_restore_a0_fixup to
        double exception vector overlapping reset vector location of secondary
        processor cores.
      - on MMUv2 cores RESET_VECTOR1_VADDR may point to uncached kernel memory
        making code overlapping depend on cache type and size, so that without
        cache or with WT cache reset vector code overwrites double exception
        code, making issue even harder to detect.
      - on MMUv3 cores RESET_VECTOR1_VADDR may point to unmapped area, as
        MMUv3 cores change virtual address map to match MMUv2 layout, but
        reset vector virtual address is given for the original MMUv3 mapping.
      - physical memory region of the secondary reset vector is not reserved
        in the physical memory map, and thus may be allocated and overwritten
        at arbitrary moment.
      
      Fix it as follows:
      
      - move window_overflow_restore_a0_fixup code to .text section.
      - define RESET_VECTOR1_VADDR so that it points to reset vector in the
        cacheable MMUv2 map for cores with MMU.
      - reserve reset vector region in the physical memory map. Drop separate
        literal section and build mxhead.S with text section literals.
      
      Cc: <stable@vger.kernel.org>
      Signed-off-by: NMax Filippov <jcmvbkbc@gmail.com>
      ab45fb14
  9. 14 8月, 2014 1 次提交
    • M
      xtensa: don't allow overflow/underflow on unaligned stack · 3cfc096e
      Max Filippov 提交于
      Double exceptions that happen during register window overflow/underflow
      are handled in the topmost stack frame, as if it was the only exception
      that occured. However unaligned access exception handler is special
      because it needs to analyze instruction that caused the exception, but
      the userspace instruction that triggered window exception is completely
      irrelevant. Unaligned data access is rather normal in the generic
      userspace code, but stack pointer manipulation must always be done by
      architecture-aware code and thus unaligned stack means a serious problem
      anyway.
      Use the default unaligned access handler that raises SIGBUS in case
      of unaligned access in window overflow/underflow handler.
      Signed-off-by: NMax Filippov <jcmvbkbc@gmail.com>
      3cfc096e
  10. 09 6月, 2014 1 次提交
    • M
      xtensa: add fixup for double exception raised in window overflow · 17290231
      Max Filippov 提交于
      There are two FIXMEs in the double exception handler 'for the extremely
      unlikely case'. This case gets hit by gcc during kernel build once in
      a few hours, resulting in an unrecoverable exception condition.
      
      Provide missing fixup routine to handle this case. Double exception
      literals now need 8 more bytes, add them to the linker script.
      
      Also replace bbsi instructions with bbsi.l as we're branching depending
      on 8th and 7th LSB-based bits of exception address.
      
      This may be tested by adding the explicit DTLB invalidation to window
      overflow handlers, like the following:
      
          --- a/arch/xtensa/kernel/vectors.S
          +++ b/arch/xtensa/kernel/vectors.S
          @@ -592,6 +592,14 @@ ENDPROC(_WindowUnderflow4)
           ENTRY_ALIGN64(_WindowOverflow8)
      
          	s32e	a0, a9, -16
          +	bbsi.l	a9, 31, 1f
          +	rsr	a0, ccount
          +	bbsi.l	a0, 4, 1f
          +	pdtlb	a0, a9
          +	idtlb	a0
          +	movi	a0, 9
          +	idtlb	a0
          +1:
          	l32e    a0, a1, -12
          	s32e    a2, a9,  -8
          	s32e    a1, a9, -12
      
      Cc: stable@vger.kernel.org
      Signed-off-by: NMax Filippov <jcmvbkbc@gmail.com>
      17290231
  11. 15 1月, 2014 1 次提交
  12. 09 5月, 2013 1 次提交
    • M
      xtensa: add MMU v3 support · e85e335f
      Max Filippov 提交于
      MMUv3 comes out of reset with identity vaddr -> paddr mapping in the TLB
      way 6:
      
      Way 6 (512 MB)
              Vaddr       Paddr       ASID  Attr RWX Cache
              ----------  ----------  ----  ---- --- -------
              0x00000000  0x00000000  0x01  0x03 RWX Bypass
              0x20000000  0x20000000  0x01  0x03 RWX Bypass
              0x40000000  0x40000000  0x01  0x03 RWX Bypass
              0x60000000  0x60000000  0x01  0x03 RWX Bypass
              0x80000000  0x80000000  0x01  0x03 RWX Bypass
              0xa0000000  0xa0000000  0x01  0x03 RWX Bypass
              0xc0000000  0xc0000000  0x01  0x03 RWX Bypass
              0xe0000000  0xe0000000  0x01  0x03 RWX Bypass
      
      This patch adds remapping code at the reset vector or at the kernel
      _start (depending on CONFIG_INITIALIZE_XTENSA_MMU_INSIDE_VMLINUX) that
      reconfigures MMUv3 as MMUv2:
      
      Way 5 (128 MB)
              Vaddr       Paddr       ASID  Attr RWX Cache
              ----------  ----------  ----  ---- --- -------
              0xd0000000  0x00000000  0x01  0x07 RWX WB
              0xd8000000  0x00000000  0x01  0x03 RWX Bypass
      Way 6 (256 MB)
              Vaddr       Paddr       ASID  Attr RWX Cache
              ----------  ----------  ----  ---- --- -------
              0xe0000000  0xf0000000  0x01  0x07 RWX WB
              0xf0000000  0xf0000000  0x01  0x03 RWX Bypass
      Signed-off-by: NMax Filippov <jcmvbkbc@gmail.com>
      Signed-off-by: NChris Zankel <chris@zankel.net>
      e85e335f
  13. 24 2月, 2013 1 次提交
  14. 04 10月, 2012 1 次提交
  15. 21 6月, 2012 1 次提交
  16. 25 3月, 2011 1 次提交
    • T
      percpu: Always align percpu output section to PAGE_SIZE · 0415b00d
      Tejun Heo 提交于
      Percpu allocator honors alignment request upto PAGE_SIZE and both the
      percpu addresses in the percpu address space and the translated kernel
      addresses should be aligned accordingly.  The calculation of the
      former depends on the alignment of percpu output section in the kernel
      image.
      
      The linker script macros PERCPU_VADDR() and PERCPU() are used to
      define this output section and the latter takes @align parameter.
      Several architectures are using @align smaller than PAGE_SIZE breaking
      percpu memory alignment.
      
      This patch removes @align parameter from PERCPU(), renames it to
      PERCPU_SECTION() and makes it always align to PAGE_SIZE.  While at it,
      add PCPU_SETUP_BUG_ON() checks such that alignment problems are
      reliably detected and remove percpu alignment comment recently added
      in workqueue.c as the condition would trigger BUG way before reaching
      there.
      
      For um, this patch raises the alignment of percpu area.  As the area
      is in .init, there shouldn't be any noticeable difference.
      
      This problem was discovered by David Howells while debugging boot
      failure on mn10300.
      Signed-off-by: NTejun Heo <tj@kernel.org>
      Acked-by: NMike Frysinger <vapier@gentoo.org>
      Cc: uclinux-dist-devel@blackfin.uclinux.org
      Cc: David Howells <dhowells@redhat.com>
      Cc: Jeff Dike <jdike@addtoit.com>
      Cc: user-mode-linux-devel@lists.sourceforge.net
      0415b00d
  17. 25 1月, 2011 1 次提交
    • T
      percpu: align percpu readmostly subsection to cacheline · 19df0c2f
      Tejun Heo 提交于
      Currently percpu readmostly subsection may share cachelines with other
      percpu subsections which may result in unnecessary cacheline bounce
      and performance degradation.
      
      This patch adds @cacheline parameter to PERCPU() and PERCPU_VADDR()
      linker macros, makes each arch linker scripts specify its cacheline
      size and use it to align percpu subsections.
      
      This is based on Shaohua's x86 only patch.
      Signed-off-by: NTejun Heo <tj@kernel.org>
      Cc: Shaohua Li <shaohua.li@intel.com>
      19df0c2f
  18. 25 9月, 2009 1 次提交
  19. 09 7月, 2009 1 次提交
    • T
      linker script: unify usage of discard definition · 023bf6f1
      Tejun Heo 提交于
      Discarded sections in different archs share some commonality but have
      considerable differences.  This led to linker script for each arch
      implementing its own /DISCARD/ definition, which makes maintaining
      tedious and adding new entries error-prone.
      
      This patch makes all linker scripts to move discard definitions to the
      end of the linker script and use the common DISCARDS macro.  As ld
      uses the first matching section definition, archs can include default
      discarded sections by including them earlier in the linker script.
      
      ia64 is notable because it first throws away some ia64 specific
      subsections and then include the rest of the sections into the final
      image, so those sections must be discarded before the inclusion.
      
      defconfig compile tested for x86, x86-64, powerpc, powerpc64, ia64,
      alpha, sparc, sparc64 and s390.  Michal Simek tested microblaze.
      Signed-off-by: NTejun Heo <tj@kernel.org>
      Acked-by: NPaul Mundt <lethal@linux-sh.org>
      Acked-by: NMike Frysinger <vapier@gentoo.org>
      Tested-by: NMichal Simek <monstr@monstr.eu>
      Cc: linux-arch@vger.kernel.org
      Cc: Michal Simek <monstr@monstr.eu>
      Cc: microblaze-uclinux@itee.uq.edu.au
      Cc: Sam Ravnborg <sam@ravnborg.org>
      Cc: Tony Luck <tony.luck@intel.com>
      023bf6f1
  20. 24 6月, 2009 1 次提交
    • T
      linker script: throw away .discard section · 405d967d
      Tejun Heo 提交于
      x86 throws away .discard section but no other archs do.  Also,
      .discard is not thrown away while linking modules.  Make every arch
      and module linking throw it away.  This will be used to define dummy
      variables for percpu declarations and definitions.
      
      This patch is based on Ivan Kokshaysky's alpha percpu patch.
      
      [ Impact: always throw away everything in .discard ]
      Signed-off-by: NTejun Heo <tj@kernel.org>
      Cc: Ivan Kokshaysky <ink@jurassic.park.msu.ru>
      Cc: Richard Henderson <rth@twiddle.net>
      Cc: Russell King <linux@arm.linux.org.uk>
      Cc: Haavard Skinnemoen <hskinnemoen@atmel.com>
      Cc: Bryan Wu <cooloney@kernel.org>
      Cc: Mikael Starvik <starvik@axis.com>
      Cc: Jesper Nilsson <jesper.nilsson@axis.com>
      Cc: David Howells <dhowells@redhat.com>
      Cc: Yoshinori Sato <ysato@users.sourceforge.jp>
      Cc: Tony Luck <tony.luck@intel.com>
      Cc: Hirokazu Takata <takata@linux-m32r.org>
      Cc: Geert Uytterhoeven <geert@linux-m68k.org>
      Cc: Michal Simek <monstr@monstr.eu>
      Cc: Ralf Baechle <ralf@linux-mips.org>
      Cc: Kyle McMartin <kyle@mcmartin.ca>
      Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org>
      Cc: Paul Mackerras <paulus@samba.org>
      Cc: Martin Schwidefsky <schwidefsky@de.ibm.com>
      Cc: Heiko Carstens <heiko.carstens@de.ibm.com>
      Cc: Paul Mundt <lethal@linux-sh.org>
      Cc: David S. Miller <davem@davemloft.net>
      Cc: Jeff Dike <jdike@addtoit.com>
      Cc: Chris Zankel <chris@zankel.net>
      Cc: Rusty Russell <rusty@rustcorp.com.au>
      Cc: Ingo Molnar <mingo@elte.hu>
      405d967d
  21. 12 5月, 2009 1 次提交
    • C
      xtensa: Fix linker script to include .literal sections · 78f3cdfa
      Chris Zankel 提交于
      Fix resembles implementation from Marc Gauthier and Piet Denaly:
      
      In the Xtensa architecture, assembly generates literals which must always
      precede the code (the L32R instruction that loads them only uses negative
      PC-relative offsets).  For any *.text section, literals are placed in a
      corresponding *.literal section.  The linker script (vmlinux.lds) must
      place these in the correct order.  It must also combine them, when the
      *.text section can be larger than L32R's 256 kB range.
      
      For example, this doesn't work:  *(.literal) *(.text) because L32R
      instructions at the end of .text can't reach the literals.
      
      The linker can solve this if they are combined in parentheses, like this:
             *(.literal .text)
      because it is now allowed mix literals in .text to bring them in range.
      
      None of this is done by standard vmlinux.lds.h macros such as TEXT_TEXT
      and INIT_TEXT.  To avoid replicating the logic of that header file, we
      instead post-process the generated linker script to convert *(xxx.text)
      to *(xxx.literal xxx.text) for the following text sections:
             .text .ref.text .*init.text .*exit.text .text.*
      using a sed script.  To do this we must override the default rule for
      vmlinux.lds (see scripts/Makefile.build and the top-level Makefile)
      to insert this extra step.
      Signed-off-by: NMarc Gauthier <marc@tensilica.com>
      Signed-off-by: NPete Delaney <piet@tensilica.com>
      Signed-off-by: NChris Zankel <chris@zankel.net>
      78f3cdfa
  22. 27 4月, 2009 1 次提交
  23. 03 4月, 2009 1 次提交
  24. 07 11月, 2008 1 次提交
  25. 14 2月, 2008 2 次提交
  26. 29 1月, 2008 1 次提交
  27. 20 7月, 2007 1 次提交
    • F
      define new percpu interface for shared data · 5fb7dc37
      Fenghua Yu 提交于
      per cpu data section contains two types of data.  One set which is
      exclusively accessed by the local cpu and the other set which is per cpu,
      but also shared by remote cpus.  In the current kernel, these two sets are
      not clearely separated out.  This can potentially cause the same data
      cacheline shared between the two sets of data, which will result in
      unnecessary bouncing of the cacheline between cpus.
      
      One way to fix the problem is to cacheline align the remotely accessed per
      cpu data, both at the beginning and at the end.  Because of the padding at
      both ends, this will likely cause some memory wastage and also the
      interface to achieve this is not clean.
      
      This patch:
      
      Moves the remotely accessed per cpu data (which is currently marked
      as ____cacheline_aligned_in_smp) into a different section, where all the data
      elements are cacheline aligned. And as such, this differentiates the local
      only data and remotely accessed data cleanly.
      Signed-off-by: NFenghua Yu <fenghua.yu@intel.com>
      Acked-by: NSuresh Siddha <suresh.b.siddha@intel.com>
      Cc: Rusty Russell <rusty@rustcorp.com.au>
      Cc: Christoph Lameter <clameter@sgi.com>
      Cc: <linux-arch@vger.kernel.org>
      Cc: "Luck, Tony" <tony.luck@intel.com>
      Cc: Andi Kleen <ak@suse.de>
      Signed-off-by: NAndrew Morton <akpm@linux-foundation.org>
      Signed-off-by: NLinus Torvalds <torvalds@linux-foundation.org>
      5fb7dc37
  28. 17 7月, 2007 1 次提交
  29. 01 6月, 2007 1 次提交
    • C
      [XTENSA] clean-up header files · de4f6e5b
      Chris Zankel 提交于
      The header files in the asm-xtensa directory are not clean and
      'make headers_check' fails. This is a first patch to fix most of
      the header files. It removes unnecessary include statements and
      adds some that are required for building the kernel. The linker
      script required some updates or the linking stage would fail.
      Signed-off-by: NChris Zankel <chris@zankel.net>
      de4f6e5b
  30. 19 5月, 2007 2 次提交
  31. 03 5月, 2007 1 次提交
  32. 12 2月, 2007 1 次提交
  33. 11 12月, 2006 2 次提交
  34. 28 10月, 2006 1 次提交
  35. 01 7月, 2006 1 次提交
  36. 13 7月, 2005 1 次提交