- 11 2月, 2016 2 次提交
-
-
由 Rex Zhu 提交于
amd_pp_dal_clock_info to amd_pp_simple_clock_info. Signed-off-by: NRex Zhu <Rex.Zhu@amd.com> Reviewed-by: NAlex Deucher <alexander.deucher@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
-
由 Eric Huang 提交于
The new sysfs interfaces: pp_num_states: Read-only, return the number of all pp states, 0 if powerplay is not available. pp_cur_state: Read-only, return the index number of current pp state. pp_force_state: Read-write, to write a power state index will switch to selected state forcedly and enable forced state mode, disable forced state mode. such as "echo >...". pp_table: Read-write, binary output, to be used to read or write the dpm table, the maximum file size is 4KB of page size. pp_dpm_sclk: Read-write, reading will return a dpm levels list, to write an index number will force powerplay to set the corresponding dpm level. pp_dpm_mclk: same as sclk. pp_dpm_pcie: same as sclk. And add new setting "manual" to the existing interface power_dpm_force_performance_level. Reviewed-by: NAlex Deucher <alexander.deucher@amd.com> Signed-off-by: NEric Huang <JinHuiEric.Huang@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
-
- 22 12月, 2015 8 次提交
-
-
由 Eric Yang 提交于
Add required structures for amd_powerplay_display_configuration_change Signed-off-by: NEric Yang <eric.yang2@amd.com>
-
由 Vitaly Prosyak 提交于
Simplify data struct for get dal power level Signed-off-by: NVitaly Prosyak <vitaly.prosyak@amd.com>
-
由 Vitaly Prosyak 提交于
Implement get dal power level and simple clock info Signed-off-by: NVitaly Prosyak <vitaly.prosyak@amd.com>
-
由 Rex Zhu 提交于
Signed-off-by: NRex Zhu <Rex.Zhu@amd.com> Signed-off-by: NDavid Rokhvarg <David.Rokhvarg@amd.com> Reviewed-by: NAlex Deucher <alexander.deucher@amd.com> Reviewed-by: NJammy Zhou <Jammy.Zhou@amd.com>
-
由 Rex Zhu 提交于
This adds the interface needed to expose powerplay fan control to sysfs via hwmon. Signed-off-by: NRex Zhu <Rex.Zhu@amd.com> Reviewed-by: NJammy Zhou <Jammy.Zhou@amd.com> Reviewed-by: NAlex Deucher <alexander.deucher@amd.com>
-
由 Rex Zhu 提交于
Interface for clock and power gating handling. Signed-off-by: NRex Zhu <Rex.Zhu@amd.com> Reviewed-by: NJammy Zhou <Jammy.Zhou@amd.com> Reviewed-by: NAlex Deucher <alexander.deucher@amd.com>
-
由 Jammy Zhou 提交于
The hwmgr handles all hardware related calls, including clock/power gating control, DPM, read and parse PPTable, etc. v5: squash in fixes v4: implement acpi's atcs function use cgs interface v3: fix code style error and add big-endian mode support. v2: use cgs interface directly in hwmgr sub-module Signed-off-by: NRex Zhu <Rex.Zhu@amd.com> Signed-off-by: NJammy Zhou <Jammy.Zhou@amd.com> Reviewed-by: NAlex Deucher <alexander.deucher@amd.com>
-
由 Alex Deucher 提交于
amdgpu_pp_ip_funcs is introduced to handle the two code paths, the legacy one and the new powerplay implementation. CONFIG_DRM_AMD_POWERPLAY kernel configuration option is introduced for the powerplay component. v4: squash in fixes v3: register debugfs file when powerplay module enable v2: add amdgpu_ucode_init_bo in hw init when amdgpu_powerplay enable. Signed-off-by: NRex Zhu <Rex.Zhu@amd.com> Signed-off-by: NJammy Zhou <Jammy.Zhou@amd.com> Reviewed-by: NAlex Deucher <alexander.deucher@amd.com>
-