Just a cleanup, to avoid duplicating parts of nv50_crtc.c's code in
the page flipping routines.
Signed-off-by: NBen Skeggs <bskeggs@redhat.com>

Signed-off-by: NBen Skeggs <bskeggs@redhat.com>

This should prevent a number of races from occuring, the most obvious of
which will be exposed when we start making use of the "display sync" evo
channel for page flipping.  The DS channel will reject any command stream
that doesn't completely agree with the current "master" state.
Signed-off-by: NBen Skeggs <bskeggs@redhat.com>

We need to be able to have the bh run while possibly spinning waiting for
the EVO notifier to signal.  This apparently happens in some circumstances
with preempt disabled, so our workqueue was never being run.
Signed-off-by: NBen Skeggs <bskeggs@redhat.com>

The nv50 display isr bh needs to be converted to a tasklet, which means
we can't sleep anymore.  The places we execute vbios init tables are
rare, and not in any way performance critical, so this isn't a huge
problem.
Signed-off-by: NBen Skeggs <bskeggs@redhat.com>

Signed-off-by: NBen Skeggs <bskeggs@redhat.com>

Signed-off-by: NBen Skeggs <bskeggs@redhat.com>

Signed-off-by: NBen Skeggs <bskeggs@redhat.com>

Signed-off-by: NBen Skeggs <bskeggs@redhat.com>

More appropriate, and we're about to be using more than just the master
EVO channel.
Signed-off-by: NBen Skeggs <bskeggs@redhat.com>

Signed-off-by: NBen Skeggs <bskeggs@redhat.com>

With cmwq, there's no reason for nouveau to use a dedicated workqueue.
Drop dev_priv->wq and use system_wq instead.  Each work item is sync
flushed when the containing structure is unregistered/destroyed.

Note that this change also makes sure that nv50_gpio_handler is not
freed while the contained work item is still running.
Signed-off-by: NTejun Heo <tj@kernel.org>
Cc: David Airlie <airlied@linux.ie>
Cc: dri-devel@lists.freedesktop.org
Signed-off-by: NBen Skeggs <bskeggs@redhat.com>

Signed-off-by: NLucas Stach <dev@lynxeye.de>
Signed-off-by: NBen Skeggs <bskeggs@redhat.com>

This gives a small, but noticeable performance gain at lower performance
levels, and unchanged at the higher ones.

With this commit, we're now using the same timeslice size as the NVIDIA
binary driver currently does, and dropping an unknown bit that NVIDIA
no longer appear to set.
Signed-off-by: NBen Skeggs <bskeggs@redhat.com>

We may well be making more use of semaphores in the future, having the
entire VM available makes requiring DMA objects for each and every
semaphore block unnecessary.
Signed-off-by: NBen Skeggs <bskeggs@redhat.com>

Evil, evil chipset.  Worst of both worlds.
Signed-off-by: NBen Skeggs <bskeggs@redhat.com>

Signed-off-by: NBen Skeggs <bskeggs@redhat.com>

Signed-off-by: NBen Skeggs <bskeggs@redhat.com>

And also, don't disable PFIFO IRQs completely whenever we recieve one,
just when we don't know about it already.
Signed-off-by: NBen Skeggs <bskeggs@redhat.com>

These are the same semaphores nvc0 will use, and they potentially allow
us to do much cooler things than our current inter-channel sync impl.

Lets switch to them where possible now for some testing.
Signed-off-by: NBen Skeggs <bskeggs@redhat.com>

Signed-off-by: NBen Skeggs <bskeggs@redhat.com>

v2. moved nv44 pciegart table back to instmem, where it's not
    accessible by userspace clients.
Signed-off-by: NBen Skeggs <bskeggs@redhat.com>

In preparation for the addition of a new nv40 backend, we'll need to be
able to distinguish between a paged dma object and the on-chip GART.
Signed-off-by: NBen Skeggs <bskeggs@redhat.com>

In preparation for the addition of a new nv40 pcie backend.
Signed-off-by: NBen Skeggs <bskeggs@redhat.com>

This reverts commit 5a893fc2.

This causes a use after free in the ttm free alloc pages path,
when it tries to get the be after the be has been destroyed.
Signed-off-by: NDave Airlie <airlied@redhat.com>

* drm-mm-cleanup:
  radeon: move blit functions to radeon_asic.h
  radeon: kill decls for inline functions
  radeon: consolidate asic-specific function decls for r600 & later
  drm/radeon: kill radeon_bo->gobj pointer
  drm/radeon: introduce gem_to_radeon_bo helper
  drm/radeon: embed struct drm_gem_object
  drm: mm: add helper to unwind scan state
  drm: mm: add api for embedding struct drm_mm_node
  drm: mm: extract node insert helper functions
  drm: mm: track free areas implicitly
  drm/nouveau: don't munge in drm_mm internals

Merge branch 'stable/ttm.pci-api.v5' of git://git.kernel.org/pub/scm/linux/kernel/git/konrad/xen into drm-next

* 'stable/ttm.pci-api.v5' of git://git.kernel.org/pub/scm/linux/kernel/git/konrad/xen:
  ttm: Include the 'struct dev' when using the DMA API.
  nouveau/ttm/PCIe: Use dma_addr if TTM has set it.
  radeon/ttm/PCIe: Use dma_addr if TTM has set it.
  ttm: Expand (*populate) to support an array of DMA addresses.
  ttm: Utilize the DMA API for pages that have TTM_PAGE_FLAG_DMA32 set.
  ttm: Introduce a placeholder for DMA (bus) addresses.

Signed-off-by: NChris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: NDave Airlie <airlied@redhat.com>

Using an order 19 drm_ht for the mmap offsets is a little obscene. That
means that will a fully populated GTT with every single object mmaped at
least once in its lifetime, there will be exactly one object in each
bucket.

Typically systems only have at most a few thousand objects, though you
may see a KDE desktop hit 50000. And most of those should never be
mapped... On my systems, just using an order 10 ht would still have an
average occupancy less than 1, so apply a small safety factor and
use an order 12 ht, like the other mmap offset ht.
Signed-off-by: NChris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: NDave Airlie <airlied@redhat.com>

... and fixup some methods to accept the constant argument.

Now that constant module arrays are loaded into read-only memory, using
const appropriately has some benefits beyond warning the programmer
about likely mistakes.
Signed-off-by: NChris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: NDave Airlie <airlied@redhat.com>

the texture checking code didn't work for block formats like s3tc,
this overhauls it to work for all types.

v2: add texture array support.
v3: add subsampled formats
Signed-off-by: NDave Airlie <airlied@redhat.com>

Nouveau doesn't have enough information at ttm_backend_func.bind() time
to implement things like tiled GART, or to keep a buffer at a constant
address in the GPU virtual address space no matter where in physical
memory it's placed.

To resolve this, nouveau will handle binding of all buffers to the GPU
itself from the move_notify() hook.  This commit ensures it's called
for all buffer moves.

Talked to Dave about the impact on radeon, which uses move_notify, it
doesn't look like anything should break there.
Signed-off-by: NBen Skeggs <bskeggs@redhat.com>
Reviewed-by: NThomas Hellstrom <thomas@shipmail.org>
Signed-off-by: NDave Airlie <airlied@redhat.com>

If there is an alpha channel, need to mask in 1's in the alpha channel
to prevent the fb from being completely transparent.
Signed-off-by: NRob Clark <rob@ti.com>
Signed-off-by: NDave Airlie <airlied@redhat.com>

Reviewed-by: NAlex Deucher <alexdeucher@gmail.com>
Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch>
Signed-off-by: NDave Airlie <airlied@redhat.com>

Reviewed-by: NAlex Deucher <alexdeucher@gmail.com>
Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch>
Signed-off-by: NDave Airlie <airlied@redhat.com>

Now all the asic specific stuff ist mostly hid in radeon_asic.*
Reviewed-by: NAlex Deucher <alexdeucher@gmail.com>
Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch>
Signed-off-by: NDave Airlie <airlied@redhat.com>

Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch>
Signed-off-by: NDave Airlie <airlied@redhat.com>

... and switch it to container_of upcasting.

v2: converted new pageflip code-paths.
Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch>
Signed-off-by: NDave Airlie <airlied@redhat.com>

Unconditionally initialize the drm gem object - it's not
worth the trouble not to for the few kernel objects.

This patch only changes the place of the drm gem object,
access is still done via pointers.

v2: Uncoditionally align the size in radeon_bo_create. At
least the r600/evergreen blit code didn't to this, angering
the paranoid gem code.
Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch>
Signed-off-by: NDave Airlie <airlied@redhat.com>