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  1. 12 6月, 2017 1 次提交
  3. 07 4月, 2017 2 次提交
  5. 08 2月, 2017 2 次提交
  7. 01 12月, 2016 1 次提交
    • N
      clocksource: Add clockevent support to NPS400 driver · 60263dcd
      由 Noam Camus 提交于 
      Till now we used clockevent from generic ARC driver.
This was enough as long as we worked with simple multicore SoC.
When we are working with multithread SoC each HW thread can be
scheduled to receive timer interrupt using timer mask register.
This patch will provide a way to control clock events per HW thread.

The design idea is that for each core there is dedicated register
(TSI) serving all 16 HW threads.
The register is a bitmask with one bit for each HW thread.
When HW thread wants that next expiration of timer interrupt will
hit it then the proper bit should be set in this dedicated register.
When timer expires all HW threads within this core which their bit
is set at the TSI register will be interrupted.

Driver can be used from device tree by:
compatible = "ezchip,nps400-timer0" <-- for clocksource
compatible = "ezchip,nps400-timer1" <-- for clockevent

Note that name convention for timer0/timer1 was taken from legacy
ARC design. This design is our base before adding HW threads.
For backward compatibility we keep "ezchip,nps400-timer" for clocksource
Signed-off-by: NNoam Camus <noamca@mellanox.com>
Acked-by: NDaniel Lezcano <daniel.lezcano@linaro.org>
Acked-by: NRob Herring <robh@kernel.org>
      60263dcd
  9. 21 10月, 2016 1 次提交
  11. 12 9月, 2016 1 次提交
  13. 09 9月, 2016 1 次提交
  15. 23 7月, 2016 1 次提交
  17. 06 7月, 2016 1 次提交
  19. 28 6月, 2016 2 次提交
  21. 09 5月, 2016 2 次提交
  23. 28 4月, 2016 1 次提交
  25. 11 2月, 2016 1 次提交
  27. 20 11月, 2015 1 次提交
  29. 13 10月, 2015 1 次提交
  31. 03 9月, 2015 1 次提交
  33. 24 7月, 2015 1 次提交
  35. 18 7月, 2015 1 次提交
  37. 23 6月, 2015 1 次提交
  39. 02 6月, 2015 2 次提交
  41. 28 5月, 2015 1 次提交
  43. 27 3月, 2015 1 次提交
  45. 04 2月, 2015 1 次提交
    • P
      Documentation: DT bindings: add more Tegra chip compatible strings · 193c9d23
      由 Paul Walmsley 提交于 
      Align compatible strings for several IP blocks present on Tegra chips
with the latest doctrine from the DT maintainers:

http://marc.info/?l=devicetree&m=142255654213019&w=2

The primary objective here is to avoid checkpatch warnings, per:

http://marc.info/?l=linux-tegra&m=142201349727836&w=2

DT binding text files have been updated for the following IP blocks:

- PCIe
- SOR
- SoC timers
- AHB "gizmo"
- APB_MISC
- pinmux control
- UART
- PWM
- I2C
- SPI
- RTC
- PMC
- eFuse
- AHCI
- HDA
- XUSB_PADCTRL
- SDHCI
- SOC_THERM
- AHUB
- I2S
- EHCI
- USB PHY

N.B. The nvidia,tegra20-timer compatible string is removed from the
nvidia,tegra30-timer.txt documentation file because it's already
mentioned in the nvidia,tegra20-timer.txt documentation file.

This second version takes into account the following requests from
Rob Herring <robherring2@gmail.com>:

- Per-IP block patches have been combined into a single patch

- Explicit documentation about which compatible strings are actually
  matched by the driver has been removed.  In its place is implicit
  documentation that loosely follows Rob's prescribed format:

  "Must contain '"nvidia,<chip>-pcie", "nvidia,tegra20-pcie"' where
   <chip> is tegra30, tegra132, ..." [...]  "You should attempt to
   document known values of <chip> if you use it"
Signed-off-by: NPaul Walmsley <paul@pwsan.com>
Cc: Alexandre Courbot <gnurou@gmail.com>
Cc: Dylan Reid <dgreid@chromium.org>
Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Cc: Hans de Goede <hdegoede@redhat.com>
Cc: Ian Campbell <ijc+devicetree@hellion.org.uk>
Cc: Jingchang Lu <jingchang.lu@freescale.com>
Cc: John Crispin <blogic@openwrt.org>
Cc: Kumar Gala <galak@codeaurora.org>
Cc: Linus Walleij <linus.walleij@linaro.org>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Mikko Perttunen <mperttunen@nvidia.com>
Cc: Murali Karicheri <m-karicheri2@ti.com>
Cc: Paul Walmsley <pwalmsley@nvidia.com>
Cc: Pawel Moll <pawel.moll@arm.com>
Cc: Peter De Schrijver <pdeschrijver@nvidia.com>
Cc: Peter Hurley <peter@hurleysoftware.com>
Cc: Sean Paul <seanpaul@chromium.org>
Cc: Stephen Warren <swarren@wwwdotorg.org>
Cc: Takashi Iwai <tiwai@suse.de>
Cc: Tejun Heo <tj@kernel.org>
Cc: "Terje Bergström" <tbergstrom@nvidia.com>
Cc: Thierry Reding <thierry.reding@gmail.com>
Cc: Tuomas Tynkkynen <ttynkkynen@nvidia.com>
Cc: Wolfram Sang <wsa@the-dreams.de>
Cc: Zhang Rui <rui.zhang@intel.com>
Cc: dri-devel@lists.freedesktop.org
Cc: linux-i2c@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
Cc: linux-pci@vger.kernel.org
Cc: linux-pm@vger.kernel.org
Cc: linux-pwm@vger.kernel.org
Cc: linux-tegra@vger.kernel.org
Acked-by: NEduardo Valentin <edubezval@gmail.com>
Signed-off-by: NRob Herring <robh@kernel.org>
      193c9d23
  47. 29 1月, 2015 2 次提交
    • B
      clocksource: devicetree: Document Conexant Digicolor timer binding · 9ff99be7
      由 Baruch Siach 提交于 
      The Conexant CX92755 SoC provides 8 32-bit timers as part of its so called
"Agent Communication" block. Timers can be configures either as free running or
one shot. Each timer has a dedicated interrupt source in the CX92755 interrupts
controller. The first timer (Timer A) can also be configured as watchdog.

This commit adds devicetree binding definition of this hardware module. The
binding defined here should be reusable for other SoCs in the Digicolor series.
Signed-off-by: NBaruch Siach <baruch@tkos.co.il>
Signed-off-by: NDaniel Lezcano <daniel.lezcano@linaro.org>
      9ff99be7
    • D
      clockevents: rockchip: Add rockchip timer for rk3288 · 468b8c4c
      由 Daniel Lezcano 提交于 
      The rk3288 board uses the architected timers and these ones are shutdown when
the cpu is powered down. There is a need of a broadcast timer in this case to
ensure proper wakeup when the cpus are in sleep mode and a timer expires.

This driver provides the basic timer functionnality as a backup for the local
timers at sleep time.

The timer belongs to the alive subsystem. It includes two programmables 64 bits
timer channels but the driver only uses 32bits. It works with two operations
mode: free running and user defined count.

Programing sequence:

1. Timer initialization:
 * Disable the timer by writing '0' to the CONTROLREG register
 * Program the timer mode by writing the mode to the CONTROLREG register
 * Set the interrupt mask

2. Setting the count value:
 * Load the count value to the registers COUNT0 and COUNT1 (not used).

3. Enable the timer
 * Write '1' to the CONTROLREG register with the mode (free running or user)
Signed-off-by: NDaniel Lezcano <daniel.lezcano@linaro.org>
Reviewed-by: NHeiko Stuebner <heiko@sntech.de>
      468b8c4c
  49. 26 11月, 2014 1 次提交
  51. 27 10月, 2014 3 次提交
  53. 29 9月, 2014 1 次提交
  55. 06 9月, 2014 3 次提交
    • S
      clocksource: sh_tmu: Document r8a7779 binding · fb0eee2f
      由 Simon Horman 提交于 
      In general Renesas hardware is not documented to the extent
where the relationship between IP blocks on different SoCs can be assumed
although they may appear to operate the same way. Furthermore the
documentation typically does not specify a version for individual
IP blocks. For these reasons a convention of using the SoC name in place
of a version and providing SoC-specific compat strings has been adopted.

Although not universally liked this convention is used in the bindings
for a number of drivers for Renesas hardware. The purpose of this patch is
to update the Renesas R-Car Timer Unit (TMU) driver to follow this
convention.
Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>
Acked-by: NGeert Uytterhoeven <geert+renesas@glider.be>
Acked-by: NLaurent Pinchart <laurent.pinchart@ideasonboard.com>

---
* I plan to follow up with a patch patch to use the new binding in the
  dtsi files for the r8a7779 SoC.
commit 471269b790aec03385dc4fb127ed7094ff83c16d

v2
* Suggestions by Mark Rutland and Sergei Shtylyov
  - Compatible strings should be "one or more" not "one" of those listed
  - Describe the generic binding as covering any MTU2 device
  - Re-order compat strings from most to least specific

v3
* Suggested by Laurent Pinchart
  - Reword in keeping with a similar though more extensive patch for CMT
      fb0eee2f
    • S
      clocksource: sh_mtu2: Document r7s72100 binding · ffd24a54
      由 Simon Horman 提交于 
      In general Renesas hardware is not documented to the extent
where the relationship between IP blocks on different SoCs can be assumed
although they may appear to operate the same way. Furthermore the
documentation typically does not specify a version for individual
IP blocks. For these reasons a convention of using the SoC name in place
of a version and providing SoC-specific compat strings has been adopted.

Although not universally liked this convention is used in the bindings
for a number of drivers for Renesas hardware. The purpose of this patch is
to update the Renesas R-Car Multi-Function Timer Pulse Unit 2 (MTU2) driver
to follow this convention.
Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>
Acked-by: NGeert Uytterhoeven <geert+renesas@glider.be>
Acked-by: NLaurent Pinchart <laurent.pinchart@ideasonboard.com>

---
* I plan to follow up with a patch patch to use the new binding in the
  dtsi files for the r7s72100 SoC.

v2
* Suggestions by Mark Rutland and Sergei Shtylyov
  - Compatible strings should be "one or more" not "one" of those listed
  - Describe the generic binding as covering any MTU2 device
  - Re-order compat strings from most to least specific

v3
* Suggested by Laurent Pinchart
  - Reword compat documentation for consistency with a more extensive
    CMT change
      ffd24a54
    • S
      clocksource: sh_cmt: Document SoC specific bindings · 01fe3aaa
      由 Simon Horman 提交于 
      In general Renesas hardware is not documented to the extent
where the relationship between IP blocks on different SoCs can be assumed
although they may appear to operate the same way. Furthermore the
documentation typically does not specify a version for individual
IP blocks. For these reasons a convention of using the SoC name in place
of a version and providing SoC-specific compat strings has been adopted.

Although not universally liked this convention is used in the bindings for
a number of drivers for Renesas hardware. The purpose of this patch is to
update the Renesas R-Car Compare Match Timer (CMT) driver to follow this
convention.
Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>
Acked-by: NGeert Uytterhoeven <geert+renesas@glider.be>
Acked-by: NMark Rutland <mark.rutland@arm.com>
Acked-by: NLaurent Pinchart <laurent.pinchart@ideasonboard.com>

---
* I plan to follow up with patches to use these new bindings in the
  dtsi files for the affected SoCs.

v2
* Reorder compat entries so more-specific entries and their fallbacks
  are grouped with the fallback entry coming last.
* Explicitly document fallback

v3
* Avoid circular dependency in documentation of fallback
  behaviour of renesas,cmt-48-gen2
* Use consistent case for SoC names in compat string descriptions
      01fe3aaa
  57. 23 7月, 2014 2 次提交