1. 12 7月, 2011 3 次提交
    • N
      KVM: nVMX: vmcs12 checks on nested entry · 7c177938
      Nadav Har'El 提交于
      This patch adds a bunch of tests of the validity of the vmcs12 fields,
      according to what the VMX spec and our implementation allows. If fields
      we cannot (or don't want to) honor are discovered, an entry failure is
      emulated.
      
      According to the spec, there are two types of entry failures: If the problem
      was in vmcs12's host state or control fields, the VMLAUNCH instruction simply
      fails. But a problem is found in the guest state, the behavior is more
      similar to that of an exit.
      Signed-off-by: NNadav Har'El <nyh@il.ibm.com>
      Signed-off-by: NMarcelo Tosatti <mtosatti@redhat.com>
      7c177938
    • N
      KVM: nVMX: Exiting from L2 to L1 · 4704d0be
      Nadav Har'El 提交于
      This patch implements nested_vmx_vmexit(), called when the nested L2 guest
      exits and we want to run its L1 parent and let it handle this exit.
      
      Note that this will not necessarily be called on every L2 exit. L0 may decide
      to handle a particular exit on its own, without L1's involvement; In that
      case, L0 will handle the exit, and resume running L2, without running L1 and
      without calling nested_vmx_vmexit(). The logic for deciding whether to handle
      a particular exit in L1 or in L0, i.e., whether to call nested_vmx_vmexit(),
      will appear in a separate patch below.
      Signed-off-by: NNadav Har'El <nyh@il.ibm.com>
      Signed-off-by: NMarcelo Tosatti <mtosatti@redhat.com>
      4704d0be
    • N
      KVM: nVMX: Success/failure of VMX instructions. · 0140caea
      Nadav Har'El 提交于
      VMX instructions specify success or failure by setting certain RFLAGS bits.
      This patch contains common functions to do this, and they will be used in
      the following patches which emulate the various VMX instructions.
      Signed-off-by: NNadav Har'El <nyh@il.ibm.com>
      Signed-off-by: NMarcelo Tosatti <mtosatti@redhat.com>
      0140caea
  2. 12 1月, 2011 3 次提交
  3. 01 8月, 2010 4 次提交
  4. 19 5月, 2010 2 次提交
  5. 01 3月, 2010 4 次提交
  6. 03 12月, 2009 1 次提交
    • Z
      KVM: VMX: Add support for Pause-Loop Exiting · 4b8d54f9
      Zhai, Edwin 提交于
      New NHM processors will support Pause-Loop Exiting by adding 2 VM-execution
      control fields:
      PLE_Gap    - upper bound on the amount of time between two successive
                   executions of PAUSE in a loop.
      PLE_Window - upper bound on the amount of time a guest is allowed to execute in
                   a PAUSE loop
      
      If the time, between this execution of PAUSE and previous one, exceeds the
      PLE_Gap, processor consider this PAUSE belongs to a new loop.
      Otherwise, processor determins the the total execution time of this loop(since
      1st PAUSE in this loop), and triggers a VM exit if total time exceeds the
      PLE_Window.
      * Refer SDM volume 3b section 21.6.13 & 22.1.3.
      
      Pause-Loop Exiting can be used to detect Lock-Holder Preemption, where one VP
      is sched-out after hold a spinlock, then other VPs for same lock are sched-in
      to waste the CPU time.
      
      Our tests indicate that most spinlocks are held for less than 212 cycles.
      Performance tests show that with 2X LP over-commitment we can get +2% perf
      improvement for kernel build(Even more perf gain with more LPs).
      Signed-off-by: NZhai Edwin <edwin.zhai@intel.com>
      Signed-off-by: NMarcelo Tosatti <mtosatti@redhat.com>
      4b8d54f9
  7. 10 9月, 2009 2 次提交
  8. 10 6月, 2009 1 次提交
    • A
      KVM: Add VT-x machine check support · a0861c02
      Andi Kleen 提交于
      VT-x needs an explicit MC vector intercept to handle machine checks in the
      hyper visor.
      
      It also has a special option to catch machine checks that happen
      during VT entry.
      
      Do these interceptions and forward them to the Linux machine check
      handler. Make it always look like user space is interrupted because
      the machine check handler treats kernel/user space differently.
      
      Thanks to Jiang Yunhong for help and testing.
      
      Cc: stable@kernel.org
      Signed-off-by: NAndi Kleen <ak@linux.intel.com>
      Signed-off-by: NHuang Ying <ying.huang@intel.com>
      Signed-off-by: NAvi Kivity <avi@redhat.com>
      a0861c02
  9. 24 3月, 2009 2 次提交
    • J
      KVM: x86: Virtualize debug registers · 42dbaa5a
      Jan Kiszka 提交于
      So far KVM only had basic x86 debug register support, once introduced to
      realize guest debugging that way. The guest itself was not able to use
      those registers.
      
      This patch now adds (almost) full support for guest self-debugging via
      hardware registers. It refactors the code, moving generic parts out of
      SVM (VMX was already cleaned up by the KVM_SET_GUEST_DEBUG patches), and
      it ensures that the registers are properly switched between host and
      guest.
      
      This patch also prepares debug register usage by the host. The latter
      will (once wired-up by the following patch) allow for hardware
      breakpoints/watchpoints in guest code. If this is enabled, the guest
      will only see faked debug registers without functionality, but with
      content reflecting the guest's modifications.
      
      Tested on Intel only, but SVM /should/ work as well, but who knows...
      
      Known limitations: Trapping on tss switch won't work - most probably on
      Intel.
      
      Credits also go to Joerg Roedel - I used his once posted debugging
      series as platform for this patch.
      Signed-off-by: NJan Kiszka <jan.kiszka@siemens.com>
      Signed-off-by: NAvi Kivity <avi@redhat.com>
      42dbaa5a
    • J
      KVM: VMX: Support for injecting software exceptions · 8ab2d2e2
      Jan Kiszka 提交于
      VMX differentiates between processor and software generated exceptions
      when injecting them into the guest. Extend vmx_queue_exception
      accordingly (and refactor related constants) so that we can use this
      service reliably for the new guest debugging framework.
      Signed-off-by: NJan Kiszka <jan.kiszka@siemens.com>
      Signed-off-by: NAvi Kivity <avi@redhat.com>
      8ab2d2e2
  10. 31 12月, 2008 4 次提交
  11. 12 11月, 2008 1 次提交
    • S
      KVM: VMX: Set IGMT bit in EPT entry · 928d4bf7
      Sheng Yang 提交于
      There is a potential issue that, when guest using pagetable without vmexit when
      EPT enabled, guest would use PAT/PCD/PWT bits to index PAT msr for it's memory,
      which would be inconsistent with host side and would cause host MCE due to
      inconsistent cache attribute.
      
      The patch set IGMT bit in EPT entry to ignore guest PAT and use WB as default
      memory type to protect host (notice that all memory mapped by KVM should be WB).
      Signed-off-by: NSheng Yang <sheng@linux.intel.com>
      Signed-off-by: NAvi Kivity <avi@redhat.com>
      928d4bf7
  12. 15 10月, 2008 3 次提交
  13. 11 9月, 2008 1 次提交
  14. 10 9月, 2008 1 次提交
  15. 20 7月, 2008 1 次提交
  16. 04 5月, 2008 4 次提交
  17. 27 4月, 2008 2 次提交
  18. 31 1月, 2008 1 次提交