1. 22 6月, 2015 3 次提交
  2. 13 6月, 2015 1 次提交
  3. 08 6月, 2015 1 次提交
  4. 21 5月, 2015 1 次提交
  5. 13 5月, 2015 1 次提交
  6. 25 4月, 2015 1 次提交
  7. 09 4月, 2015 2 次提交
  8. 03 4月, 2015 2 次提交
  9. 01 4月, 2015 5 次提交
    • K
      IRQCHIP: Add new driver for BCM7038-style level 1 interrupt controllers · 5f7f0317
      Kevin Cernekee 提交于
      This is the main peripheral IRQ controller on the BCM7xxx MIPS chips;
      it has the following characteristics:
      
       - 64 to 160+ level IRQs
       - Atomic set/clear registers
       - Reasonably predictable register layout (N status words, then N
         mask status words, then N mask set words, then N mask clear words)
       - SMP affinity supported on most systems
       - Typically connected to MIPS IRQ 2,3,2,3 on CPUs 0,1,2,3
      
      This driver registers one IRQ domain and one IRQ chip to cover all
      instances of the block.  Up to 4 instances of the block may appear, as
      it supports 4-way IRQ affinity on BCM7435.
      
      The same block exists on the ARM BCM7xxx chips, but typically the ARM GIC
      is used instead.  So this driver is primarily intended for MIPS STB chips.
      Signed-off-by: NKevin Cernekee <cernekee@gmail.com>
      Cc: f.fainelli@gmail.com
      Cc: jaedon.shin@gmail.com
      Cc: abrestic@chromium.org
      Cc: tglx@linutronix.de
      Cc: jason@lakedaemon.net
      Cc: jogo@openwrt.org
      Cc: arnd@arndb.de
      Cc: computersforpeace@gmail.com
      Cc: linux-mips@linux-mips.org
      Cc: devicetree@vger.kernel.org
      Cc: linux-kernel@vger.kernel.org
      Patchwork: https://patchwork.linux-mips.org/patch/8844/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
      5f7f0317
    • K
      IRQCHIP: bcm7120-l2: Add support for BCM3380-style controllers · 7b7230e7
      Kevin Cernekee 提交于
      These controllers support multiple enable/status pairs (64+ IRQs),
      can put the enable/status words at different offsets, and do not
      support multiple parent IRQs.
      Signed-off-by: NKevin Cernekee <cernekee@gmail.com>
      Cc: f.fainelli@gmail.com
      Cc: jaedon.shin@gmail.com
      Cc: abrestic@chromium.org
      Cc: tglx@linutronix.de
      Cc: jason@lakedaemon.net
      Cc: jogo@openwrt.org
      Cc: arnd@arndb.de
      Cc: computersforpeace@gmail.com
      Cc: linux-mips@linux-mips.org
      Cc: devicetree@vger.kernel.org
      Cc: linux-kernel@vger.kernel.org
      Patchwork: https://patchwork.linux-mips.org/patch/8843/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
      7b7230e7
    • K
      IRQCHIP: bcm7120-l2: Split STB-specific logic into its own function · ca40f1b2
      Kevin Cernekee 提交于
      The BCM7xxx instances of this block (listed in the register manual as
      simply "IRQ0") all have the following items in common:
      
       - brcm,int-map-mask: for routing different bits in the L2 to different
         parent IRQs
      
       - brcm,int-fwd-mask: for hardwiring certain IRQs to bypass the L2 and
         use dedicated L1 lines
      
       - one enable/status pair (32 bits only)
      
      Much of the driver code can be shared with BCM3380-style controllers, but
      in order to do this cleanly, let's split out the BCM7xxx-specific logic
      first.
      Signed-off-by: NKevin Cernekee <cernekee@gmail.com>
      Cc: f.fainelli@gmail.com
      Cc: jaedon.shin@gmail.com
      Cc: abrestic@chromium.org
      Cc: tglx@linutronix.de
      Cc: jason@lakedaemon.net
      Cc: jogo@openwrt.org
      Cc: arnd@arndb.de
      Cc: computersforpeace@gmail.com
      Cc: linux-mips@linux-mips.org
      Cc: devicetree@vger.kernel.org
      Cc: linux-kernel@vger.kernel.org
      Patchwork: https://patchwork.linux-mips.org/patch/8842/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
      ca40f1b2
    • K
      IRQCHIP: bcm7120-l2: Refactor driver for arbitrary IRQEN/IRQSTAT offsets · 5b5468cf
      Kevin Cernekee 提交于
      Currently the driver assumes that REG_BASE+0x00 is the IRQ enable mask,
      and REG_BASE+0x04 is the IRQ status mask.  This is true on BCM3384 and
      BCM7xxx, but it is not true for some of the controllers found on BCM63xx
      chips.  So we will change a couple of key assumptions:
      
       - Don't assume that both the IRQEN and IRQSTAT registers will be
         covered by a single ioremap() operation.
      
       - Don't assume any particular ordering (IRQSTAT might show up before
         IRQEN on some chips).
      
       - For an L2 controller with >=64 IRQs, don't assume that every
         IRQEN/IRQSTAT pair will use the same register spacing.
      
      This patch changes the "plumbing" but doesn't yet provide a way for users
      to instantiate a controller with arbitrary IRQEN/IRQSTAT offsets.
      Signed-off-by: NKevin Cernekee <cernekee@gmail.com>
      Cc: f.fainelli@gmail.com
      Cc: jaedon.shin@gmail.com
      Cc: abrestic@chromium.org
      Cc: tglx@linutronix.de
      Cc: jason@lakedaemon.net
      Cc: jogo@openwrt.org
      Cc: computersforpeace@gmail.com
      Cc: linux-mips@linux-mips.org
      Cc: devicetree@vger.kernel.org
      Cc: linux-kernel@vger.kernel.org
      Patchwork: https://patchwork.linux-mips.org/patch/8841/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
      5b5468cf
    • B
      IRQCHIP: brcmstb-l2: don't clear wakeable interrupts at init time · c9ae71e0
      Brian Norris 提交于
      Wakeable interrupts might be pending at boot/init time, because wakeup
      interrupts might have triggered a resume from S5. So don't clear such
      wakeups.
      
      This means that any driver which requests a wakeable interrupt bit
      should be prepared to handle an interrupt as soon as they call
      request_irq(). (This is technically already the correct development
      practice, but some drivers probably expect not to receive interrupts
      until they have performed some I/O.)
      Signed-off-by: NBrian Norris <computersforpeace@gmail.com>
      Signed-off-by: NKevin Cernekee <cernekee@gmail.com>
      Cc: f.fainelli@gmail.com
      Cc: jaedon.shin@gmail.com
      Cc: abrestic@chromium.org
      Cc: tglx@linutronix.de
      Cc: jason@lakedaemon.net
      Cc: jogo@openwrt.org
      Cc: arnd@arndb.de
      Cc: computersforpeace@gmail.com
      Cc: linux-mips@linux-mips.org
      Cc: devicetree@vger.kernel.org
      Cc: linux-kernel@vger.kernel.org
      Patchwork: https://patchwork.linux-mips.org/patch/8840/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
      c9ae71e0
  10. 31 3月, 2015 4 次提交
  11. 30 3月, 2015 6 次提交
  12. 26 3月, 2015 2 次提交
  13. 23 3月, 2015 3 次提交
  14. 15 3月, 2015 5 次提交
  15. 08 3月, 2015 3 次提交