1. 13 10月, 2016 1 次提交
  2. 10 10月, 2016 2 次提交
  3. 04 10月, 2016 1 次提交
  4. 29 9月, 2016 1 次提交
  5. 27 9月, 2016 1 次提交
  6. 23 9月, 2016 1 次提交
    • P
      drm/i915/fbc: disable FBC on FIFO underruns · 61a585d6
      Paulo Zanoni 提交于
      Ever since I started working on FBC I was already aware that FBC can
      really amplify the FIFO underrun symptoms. On systems where FIFO
      underruns were harmless error messages, enabling FBC would cause the
      underruns to give black screens.
      
      We recently tried to enable FBC on Haswell and got reports of a system
      that would hang after some hours of uptime, and the first bad commit
      was the one that enabled FBC. We also observed that this system had
      FIFO underrun error messages on its dmesg. Although we don't have any
      evidence that fixing the underruns would solve the bug and make FBC
      work properly on this machine, IMHO it's better if we minimize the
      amount of possible problems by just giving up FBC whenever we detect
      an underrun.
      
      v2: New version, different implementation and commit message.
      v3: Clarify the fact that we run from an IRQ handler (Chris).
      v4: Also add the underrun_detected check at can_choose() to avoid
          misleading dmesg messages (DK).
      v5: Fix Engrish, use READ_ONCE on the unlocked read (Chris).
      
      Cc: Stefan Richter <stefanr@s5r6.in-berlin.de>
      Cc: Lyude <cpaul@redhat.com>
      Cc: stevenhoneyman@gmail.com <stevenhoneyman@gmail.com>
      Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
      Cc: Chris Wilson <chris@chris-wilson.co.uk>
      Signed-off-by: NPaulo Zanoni <paulo.r.zanoni@intel.com>
      Reviewed-by: NChris Wilson <chris@chris-wilson.co.uk>
      Reviewed-by: NDhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
      Link: http://patchwork.freedesktop.org/patch/msgid/1473773937-19758-1-git-send-email-paulo.r.zanoni@intel.com
      61a585d6
  7. 22 9月, 2016 3 次提交
  8. 20 9月, 2016 1 次提交
  9. 15 9月, 2016 1 次提交
  10. 10 9月, 2016 2 次提交
  11. 09 9月, 2016 1 次提交
  12. 08 9月, 2016 2 次提交
  13. 07 9月, 2016 1 次提交
  14. 25 8月, 2016 1 次提交
    • L
      drm/i915/skl: Update DDB values atomically with wms/plane attrs · 27082493
      Lyude 提交于
      Now that we can hook into update_crtcs and control the order in which we
      update CRTCs at each modeset, we can finish the final step of fixing
      Skylake's watermark handling by performing DDB updates at the same time
      as plane updates and watermark updates.
      
      The first major change in this patch is skl_update_crtcs(), which
      handles ensuring that we order each CRTC update in our atomic commits
      properly so that they honor the DDB flush order.
      
      The second major change in this patch is the order in which we flush the
      pipes. While the previous order may have worked, it can't be used in
      this approach since it no longer will do the right thing. For example,
      using the old ddb flush order:
      
      We have pipes A, B, and C enabled, and we're disabling C. Initial ddb
      allocation looks like this:
      
      |   A   |   B   |xxxxxxx|
      
      Since we're performing the ddb updates after performing any CRTC
      disablements in intel_atomic_commit_tail(), the space to the right of
      pipe B is unallocated.
      
      1. Flush pipes with new allocation contained into old space. None
         apply, so we skip this
      2. Flush pipes having their allocation reduced, but overlapping with a
         previous allocation. None apply, so we also skip this
      3. Flush pipes that got more space allocated. This applies to A and B,
         giving us the following update order: A, B
      
      This is wrong, since updating pipe A first will cause it to overlap with
      B and potentially burst into flames. Our new order (see the code
      comments for details) would update the pipes in the proper order: B, A.
      
      As well, we calculate the order for each DDB update during the check
      phase, and reference it later in the commit phase when we hit
      skl_update_crtcs().
      
      This long overdue patch fixes the rest of the underruns on Skylake.
      
      Changes since v1:
       - Add skl_ddb_entry_write() for cursor into skl_write_cursor_wm()
      Changes since v2:
       - Use the method for updating CRTCs that Ville suggested
       - In skl_update_wm(), only copy the watermarks for the crtc that was
         passed to us
      Changes since v3:
       - Small comment fix in skl_ddb_allocation_overlaps()
      Changes since v4:
       - Remove the second loop in intel_update_crtcs() and use Ville's
         suggestion for updating the ddb allocations in the right order
       - Get rid of the second loop and just use the ddb state as it updates
         to determine what order to update everything in (thanks for the
         suggestion Ville)
       - Simplify skl_ddb_allocation_overlaps()
       - Split actual overlap checking into it's own helper
      
      Fixes: 0e8fb7ba ("drm/i915/skl: Flush the WM configuration")
      Fixes: 8211bd5b ("drm/i915/skl: Program the DDB allocation")
      [omitting CC for stable, since this patch will need to be changed for
      such backports first]
      
      Testcase: kms_cursor_legacy
      Testcase: plane-all-modeset-transition
      Signed-off-by: NLyude <cpaul@redhat.com>
      Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
      Cc: Daniel Vetter <daniel.vetter@intel.com>
      Cc: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
      Cc: Hans de Goede <hdegoede@redhat.com>
      Cc: Matt Roper <matthew.d.roper@intel.com>
      Signed-off-by: NMaarten Lankhorst <maarten.lankhorst@linux.intel.com>
      Link: http://patchwork.freedesktop.org/patch/msgid/1471961565-28540-2-git-send-email-cpaul@redhat.com
      27082493
  15. 24 8月, 2016 1 次提交
  16. 23 8月, 2016 5 次提交
  17. 22 8月, 2016 2 次提交
    • L
      drm/i915/skl: Add support for the SAGV, fix underrun hangs · f4033726
      Lyude 提交于
      Since the watermark calculations for Skylake are still broken, we're apt
      to hitting underruns very easily under multi-monitor configurations.
      While it would be lovely if this was fixed, it's not. Another problem
      that's been coming from this however, is the mysterious issue of
      underruns causing full system hangs. An easy way to reproduce this with
      a skylake system:
      
      - Get a laptop with a skylake GPU, and hook up two external monitors to
        it
      - Move the cursor from the built-in LCD to one of the external displays
        as quickly as you can
      - You'll get a few pipe underruns, and eventually the entire system will
        just freeze.
      
      After doing a lot of investigation and reading through the bspec, I
      found the existence of the SAGV, which is responsible for adjusting the
      system agent voltage and clock frequencies depending on how much power
      we need. According to the bspec:
      
      "The display engine access to system memory is blocked during the
       adjustment time. SAGV defaults to enabled. Software must use the
       GT-driver pcode mailbox to disable SAGV when the display engine is not
       able to tolerate the blocking time."
      
      The rest of the bspec goes on to explain that software can simply leave
      the SAGV enabled, and disable it when we use interlaced pipes/have more
      then one pipe active.
      
      Sure enough, with this patchset the system hangs resulting from pipe
      underruns on Skylake have completely vanished on my T460s. Additionally,
      the bspec mentions turning off the SAGV	with more then one pipe enabled
      as a workaround for display underruns. While this patch doesn't entirely
      fix that, it looks like it does improve the situation a little bit so
      it's likely this is going to be required to make watermarks on Skylake
      fully functional.
      
      This will still need additional work in the future: we shouldn't be
      enabling the SAGV if any of the currently enabled planes can't enable WM
      levels that introduce latencies >= 30 µs.
      
      Changes since v11:
       - Add skl_can_enable_sagv()
       - Make sure we don't enable SAGV when not all planes can enable
         watermarks >= the SAGV engine block time. I was originally going to
         save this for later, but I recently managed to run into a machine
         that was having problems with a single pipe configuration + SAGV.
       - Make comparisons to I915_SKL_SAGV_NOT_CONTROLLED explicit
       - Change I915_SAGV_DYNAMIC_FREQ to I915_SAGV_ENABLE
       - Move printks outside of mutexes
       - Don't print error messages twice
      Changes since v10:
       - Apparently sandybridge_pcode_read actually writes values and reads
         them back, despite it's misleading function name. This means we've
         been doing this mostly wrong and have been writing garbage to the
         SAGV control. Because of this, we no longer attempt to read the SAGV
         status during initialization (since there are no helpers for this).
       - mlankhorst noticed that this patch was breaking on some very early
         pre-release Skylake machines, which apparently don't allow you to
         disable the SAGV. To prevent machines from failing tests due to SAGV
         errors, if the first time we try to control the SAGV results in the
         mailbox indicating an invalid command, we just disable future attempts
         to control the SAGV state by setting dev_priv->skl_sagv_status to
         I915_SKL_SAGV_NOT_CONTROLLED and make a note of it in dmesg.
       - Move mutex_unlock() a little higher in skl_enable_sagv(). This
         doesn't actually fix anything, but lets us release the lock a little
         sooner since we're finished with it.
      Changes since v9:
       - Only enable/disable sagv on Skylake
      Changes since v8:
       - Add intel_state->modeset guard to the conditional for
         skl_enable_sagv()
      Changes since v7:
       - Remove GEN9_SAGV_LOW_FREQ, replace with GEN9_SAGV_IS_ENABLED (that's
         all we use it for anyway)
       - Use GEN9_SAGV_IS_ENABLED instead of 0x1 for clarification
       - Fix a styling error that snuck past me
      Changes since v6:
       - Protect skl_enable_sagv() with intel_state->modeset conditional in
         intel_atomic_commit_tail()
      Changes since v5:
       - Don't use is_power_of_2. Makes things confusing
       - Don't use the old state to figure out whether or not to
         enable/disable the sagv, use the new one
       - Split the loop in skl_disable_sagv into it's own function
       - Move skl_sagv_enable/disable() calls into intel_atomic_commit_tail()
      Changes since v4:
       - Use is_power_of_2 against active_crtcs to check whether we have > 1
         pipe enabled
       - Fix skl_sagv_get_hw_state(): (temp & 0x1) indicates disabled, 0x0
         enabled
       - Call skl_sagv_enable/disable() from pre/post-plane updates
      Changes since v3:
       - Use time_before() to compare timeout to jiffies
      Changes since v2:
       - Really apply minor style nitpicks to patch this time
      Changes since v1:
       - Added comments about this probably being one of the requirements to
         fixing Skylake's watermark issues
       - Minor style nitpicks from Matt Roper
       - Disable these functions on Broxton, since it doesn't have an SAGV
      Signed-off-by: NLyude <cpaul@redhat.com>
      Cc: Matt Roper <matthew.d.roper@intel.com>
      Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
      Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
      Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
      Cc: stable@vger.kernel.org
      Signed-off-by: NMaarten Lankhorst <maarten.lankhorst@linux.intel.com>
      Link: http://patchwork.freedesktop.org/patch/msgid/1471463761-26796-3-git-send-email-cpaul@redhat.com
      [mlankhorst: ENOSYS -> ENXIO, whitespace fixes]
      
      (cherry picked from commit 656d1b89)
      Signed-off-by: NJani Nikula <jani.nikula@intel.com>
      f4033726
    • L
      drm/i915/skl: Add support for the SAGV, fix underrun hangs · 656d1b89
      Lyude 提交于
      Since the watermark calculations for Skylake are still broken, we're apt
      to hitting underruns very easily under multi-monitor configurations.
      While it would be lovely if this was fixed, it's not. Another problem
      that's been coming from this however, is the mysterious issue of
      underruns causing full system hangs. An easy way to reproduce this with
      a skylake system:
      
      - Get a laptop with a skylake GPU, and hook up two external monitors to
        it
      - Move the cursor from the built-in LCD to one of the external displays
        as quickly as you can
      - You'll get a few pipe underruns, and eventually the entire system will
        just freeze.
      
      After doing a lot of investigation and reading through the bspec, I
      found the existence of the SAGV, which is responsible for adjusting the
      system agent voltage and clock frequencies depending on how much power
      we need. According to the bspec:
      
      "The display engine access to system memory is blocked during the
       adjustment time. SAGV defaults to enabled. Software must use the
       GT-driver pcode mailbox to disable SAGV when the display engine is not
       able to tolerate the blocking time."
      
      The rest of the bspec goes on to explain that software can simply leave
      the SAGV enabled, and disable it when we use interlaced pipes/have more
      then one pipe active.
      
      Sure enough, with this patchset the system hangs resulting from pipe
      underruns on Skylake have completely vanished on my T460s. Additionally,
      the bspec mentions turning off the SAGV	with more then one pipe enabled
      as a workaround for display underruns. While this patch doesn't entirely
      fix that, it looks like it does improve the situation a little bit so
      it's likely this is going to be required to make watermarks on Skylake
      fully functional.
      
      This will still need additional work in the future: we shouldn't be
      enabling the SAGV if any of the currently enabled planes can't enable WM
      levels that introduce latencies >= 30 µs.
      
      Changes since v11:
       - Add skl_can_enable_sagv()
       - Make sure we don't enable SAGV when not all planes can enable
         watermarks >= the SAGV engine block time. I was originally going to
         save this for later, but I recently managed to run into a machine
         that was having problems with a single pipe configuration + SAGV.
       - Make comparisons to I915_SKL_SAGV_NOT_CONTROLLED explicit
       - Change I915_SAGV_DYNAMIC_FREQ to I915_SAGV_ENABLE
       - Move printks outside of mutexes
       - Don't print error messages twice
      Changes since v10:
       - Apparently sandybridge_pcode_read actually writes values and reads
         them back, despite it's misleading function name. This means we've
         been doing this mostly wrong and have been writing garbage to the
         SAGV control. Because of this, we no longer attempt to read the SAGV
         status during initialization (since there are no helpers for this).
       - mlankhorst noticed that this patch was breaking on some very early
         pre-release Skylake machines, which apparently don't allow you to
         disable the SAGV. To prevent machines from failing tests due to SAGV
         errors, if the first time we try to control the SAGV results in the
         mailbox indicating an invalid command, we just disable future attempts
         to control the SAGV state by setting dev_priv->skl_sagv_status to
         I915_SKL_SAGV_NOT_CONTROLLED and make a note of it in dmesg.
       - Move mutex_unlock() a little higher in skl_enable_sagv(). This
         doesn't actually fix anything, but lets us release the lock a little
         sooner since we're finished with it.
      Changes since v9:
       - Only enable/disable sagv on Skylake
      Changes since v8:
       - Add intel_state->modeset guard to the conditional for
         skl_enable_sagv()
      Changes since v7:
       - Remove GEN9_SAGV_LOW_FREQ, replace with GEN9_SAGV_IS_ENABLED (that's
         all we use it for anyway)
       - Use GEN9_SAGV_IS_ENABLED instead of 0x1 for clarification
       - Fix a styling error that snuck past me
      Changes since v6:
       - Protect skl_enable_sagv() with intel_state->modeset conditional in
         intel_atomic_commit_tail()
      Changes since v5:
       - Don't use is_power_of_2. Makes things confusing
       - Don't use the old state to figure out whether or not to
         enable/disable the sagv, use the new one
       - Split the loop in skl_disable_sagv into it's own function
       - Move skl_sagv_enable/disable() calls into intel_atomic_commit_tail()
      Changes since v4:
       - Use is_power_of_2 against active_crtcs to check whether we have > 1
         pipe enabled
       - Fix skl_sagv_get_hw_state(): (temp & 0x1) indicates disabled, 0x0
         enabled
       - Call skl_sagv_enable/disable() from pre/post-plane updates
      Changes since v3:
       - Use time_before() to compare timeout to jiffies
      Changes since v2:
       - Really apply minor style nitpicks to patch this time
      Changes since v1:
       - Added comments about this probably being one of the requirements to
         fixing Skylake's watermark issues
       - Minor style nitpicks from Matt Roper
       - Disable these functions on Broxton, since it doesn't have an SAGV
      Signed-off-by: NLyude <cpaul@redhat.com>
      Cc: Matt Roper <matthew.d.roper@intel.com>
      Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
      Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
      Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
      Cc: stable@vger.kernel.org
      Signed-off-by: NMaarten Lankhorst <maarten.lankhorst@linux.intel.com>
      Link: http://patchwork.freedesktop.org/patch/msgid/1471463761-26796-3-git-send-email-cpaul@redhat.com
      [mlankhorst: ENOSYS -> ENXIO, whitespace fixes]
      656d1b89
  18. 19 8月, 2016 1 次提交
  19. 15 8月, 2016 1 次提交
  20. 11 8月, 2016 6 次提交
  21. 10 8月, 2016 1 次提交
  22. 09 8月, 2016 2 次提交
  23. 06 8月, 2016 1 次提交
  24. 05 8月, 2016 1 次提交