- 05 5月, 2015 1 次提交
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由 Suman Anna 提交于
The L3 Error handling on OMAP5 for the most part is very similar to that of OMAP4, and had leveraged common data structures and register layout definitions so far. Upon closer inspection, there are a few minor differences causing an incorrect decoding and reporting of the master NIU upon an error: 1. The L3_TARG_STDERRLOG_MSTADDR.STDERRLOG_MSTADDR occupies 11 bits on OMAP5 as against 8 bits on OMAP4, with the master NIU connID encoded in the 6 MSBs of the STDERRLOG_MSTADDR field. 2. The CLK3 FlagMux component has 1 input source on OMAP4 and 3 input sources on OMAP5. The common DEBUGSS source is at a different input on each SoC. Fix the above issues by using a OMAP5-specific compatible property and using SoC-specific data where there are differences. Signed-off-by: NSuman Anna <s-anna@ti.com> Acked-by: NNishanth Menon <nm@ti.com> Signed-off-by: NTony Lindgren <tony@atomide.com>
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- 06 5月, 2014 2 次提交
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由 Afzal Mohammed 提交于
Add AM4372 information to handle L3 error. AM4372 has two clk domains 100f and 200s. Provide flagmux and data associated with it. NOTE: Timeout doesn't have STDERRLOG_MAIN register. And per hardware team, L3 timeout error cannot be cleared the normal way (by setting bit 31 in STDERRLOG_MAIN), instead it may be required to do system reset. L3 error handler can't help in such scenarios. Hence indicate timeout target offset as L3_TARGET_NOT_SUPPORTED as done for undocumented bits. Signed-off-by: NDave Gerlach <d-gerlach@ti.com> Signed-off-by: NAfzal Mohammed <afzal@ti.com> Signed-off-by: NSekhar Nori <nsekhar@ti.com> Signed-off-by: NNishanth Menon <nm@ti.com> Acked-by: NSantosh Shilimkar <santosh.shilimkar@ti.com> Acked-by: NPeter Ujfalusi <peter.ujfalusi@ti.com> Tested-by: NDarren Etheridge <detheridge@ti.com> Tested-by: NSekhar Nori <nsekhar@ti.com>
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由 Rajendra Nayak 提交于
DRA7 is distinctly different from OMAP4 in terms of masters and clock domain organization. There two main clock domains which is divided as follows: <0x44000000 0x1000000> is clk1 and clk2 is the sub clock domain <0x45000000 0x1000> is clk3 Add all the data needed to handle L3 error handling on DRA7 devices and mark clk2 as subdomain and provide a compatible flag for functionality. Other than the data difference the hardware blocks involved are essentially the same. Signed-off-by: NRajendra Nayak <rnayak@ti.com> [nm@ti.com: bugfixes and generic improvements, documentation] Signed-off-by: NNishanth Menon <nm@ti.com> Acked-by: NSantosh Shilimkar <santosh.shilimkar@ti.com> Acked-by: NPeter Ujfalusi <peter.ujfalusi@ti.com> Tested-by: NDarren Etheridge <detheridge@ti.com> Tested-by: NSekhar Nori <nsekhar@ti.com>
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- 09 4月, 2013 1 次提交
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由 Santosh Shilimkar 提交于
OMAP L3 driver needs reg address space for its operation and hence its a required property. Signed-off-by: NSantosh Shilimkar <santosh.shilimkar@ti.com> Signed-off-by: NBenoit Cousson <benoit.cousson@linaro.org>
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- 05 10月, 2011 1 次提交
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由 Benoit Cousson 提交于
Add device-tree support for the l3-noc driver. Use platform_driver_register to defer the probing at device init time. Add documentation for the l3-noc bindings. Signed-off-by: NBenoit Cousson <b-cousson@ti.com> Cc: Tony Lindgren <tony@atomide.com> Cc: Santosh Shilimkar <santosh.shilimkar@ti.com>
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