- 30 6月, 2008 1 次提交
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由 Paul Mackerras 提交于
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- 28 6月, 2008 1 次提交
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由 Kumar Gala 提交于
Added DMA nodes for the elo/elo-plus DMA engines. Renamed the interrupt controller alias in mpc832x_rdb.dts to ipic so that its the same as all the other boards. Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
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- 26 6月, 2008 9 次提交
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由 Kumar Gala 提交于
This patch is based on work done by Madhvesh. R. Sulibhavi back in March 2007. We refactor some of the single step handling since it differs between "classic" and "booke" powerpc cores. Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
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由 Kumar Gala 提交于
* Mark __flush_icache_range as a function that can't be probed since its used by the kprobe code. * Fix an issue with single stepping and async exceptions. We need to ensure that we dont get an async exception (external, decrementer, etc) while we are attempting to single step the probe point. Added a check to ensure we only handle a single step if its really intended for the instruction in question. Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
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由 Anton Vorontsov 提交于
It was discussed that global arch_initcall() is preferred way to probe QE GPIOs, so let's use it. Signed-off-by: NAnton Vorontsov <avorontsov@ru.mvista.com> Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
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由 Vitaly Bordug 提交于
Ports B and C pins programming is changed to get SCC2 UART and FCC3 ethernet work. Signed-off-by: NVitaly Bordug <vitb@kernel.crashing.org> Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
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由 Kumar Gala 提交于
Now that arch/ppc is gone we always define CONFIG_PPC_CPM_NEW_BINDING so we can remove all the code associated with !CONFIG_PPC_CPM_NEW_BINDING. Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
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由 Kumar Gala 提交于
Now that arch/ppc is gone we always define CONFIG_PPC_CPM_NEW_BINDING so we can remove all the code associated with !CONFIG_PPC_CPM_NEW_BINDING. Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
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由 Kumar Gala 提交于
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
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由 Kumar Gala 提交于
If we have an L2CSR register (e500mc) we need to flush the L2 before going to nap. We use the HW flush mechanism provided in that register. The code reuses the CPU_FTR_604_PERF_MON bit as it is no longer used by any code in the kernel. Additionally we didn't reuse the exist L2CR feature bit as this is intended for the 7xxx L2CR register and L2CSR is part of the new Freescale "Book-E" registers. Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
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由 Kumar Gala 提交于
The e500 core enter DOZE/NAP power-saving modes when the core go to cpu_idle routine. The power management default running mode is DOZE, If the user echo 1 > /proc/sys/kernel/powersave-nap the system will change to NAP running mode. Signed-off-by: NDave Liu <daveliu@freescale.com> Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
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- 19 6月, 2008 1 次提交
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由 Kumar Gala 提交于
The new e500mc core from Freescale is based on the e500v2 but with the following changes: * Supports only the Enhanced Debug Architecture (DSRR0/1, etc) * Floating Point * No SPE * Supports lwsync * Doorbell Exceptions * Hypervisor * Cache line size is now 64-bytes (e500v1/v2 have a 32-byte cache line) Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
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- 18 6月, 2008 1 次提交
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由 Josh Boyer 提交于
The 440EPx/GRx chips don't support PCI MRM commands. Drivers determine this by looking for a zero value in the PCI cache line size register. However, some drivers write to this register upon initialization. This can cause MRMs to be used on these chips, which may cause deadlocks on PLB4. The workaround implemented here introduces a new indirect_type flag, called PPC_INDIRECT_TYPE_BROKEN_MRM. This is set in the pci_controller structure in the pci fixup function for 4xx PCI bridges by determining if the bridge is compatible with 440EPx/GRx. The flag is checked in the indirect_write_config function, and forces any writes to the PCI_CACHE_LINE_SIZE register to be zero, which will disable MRMs for these chips. A similar workaround has been tested by AMCC on various PCI cards, such as the Silicon Image ATA card and Intel E1000 GIGE card. Hangs were seen with the Silicon Image card, and MRMs were seen on the bus with a PCI analyzer. With the workaround in place, the card functioned properly and only Memory Reads were seen on the bus with the analyzer. Acked-by: NStefan Roese <sr@denx.de> Signed-off-by: NJosh Boyer <jwboyer@linux.vnet.ibm.com>
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- 16 6月, 2008 1 次提交
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由 Jerone Young 提交于
This takes values from the PowerPC ISA BookIII-E specifications that are for DBCR0. Many of these values are different from those currently specified, which are for the ppc405. Also added some bookE definitions for DBCR1 & DBCR2. [ galak@kernel.crashing.org: Added aliases to 40x DBCR0 to match Book-E, Added enhanced debug DBCR0/DBSR _CIRPT and _CRET defines and DBSR IRPT and RET. ] Signed-off-by: NJerone Young <jyoung5@us.ibm.com> Acked-by: NJosh Boyer <jwboyer@linux.vnet.ibm.com> Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
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- 12 6月, 2008 2 次提交
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由 Kumar Gala 提交于
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
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由 Anton Vorontsov 提交于
This patch fixes following section mismatch: WARNING: arch/powerpc/sysdev/built-in.o(.text+0x11d8): Section mismatch in reference from the function qe_reset() to the function .init.text:cpm_muram_init() Signed-off-by: NAnton Vorontsov <avorontsov@ru.mvista.com> Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
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- 11 6月, 2008 9 次提交
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由 Giuseppe Coviello 提交于
This makes the sam440ep.dts dts-v1 compliant. Signed-off-by: NGiuseppe Coviello <gicoviello@gmail.com> Signed-off-by: NJosh Boyer <jwboyer@linux.vnet.ibm.com>
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由 Giuseppe Coviello 提交于
The Sam440ep is an high customizable general purpose mini-itx board, based on the AMCC 440EP and with a LatticeXP FPGA onboard. It's poduced by ACube Systems Srl (Bassano del Grappa, Italy), http://www.acube-systems.biz. Signed-off-by: NGiuseppe Coviello <gicoviello@gmail.com> Signed-off-by: NJosh Boyer <jwboyer@linux.vnet.ibm.com>
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由 Stefan Roese 提交于
This patch add a check to the PPC4xx PCIe driver to detect if the port is disabled via the device-tree. This is needed for the AMCC Canyonlands board which has an option to either select 2 PCIe ports or 1 PCIe port and one SATA port. The SATA port and the 1st PCIe port pins are multiplexed so we can't start both drivers. Signed-off-by: NStefan Roese <sr@denx.de> Acked-by: NBenjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: NJosh Boyer <jwboyer@linux.vnet.ibm.com>
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由 Valentine Barshak 提交于
The "ndfc-chip" device doesn't need any resources. All resources are handled by the "ndfc-nand" device. Registering the same memory resource twice causes "cat /proc/iomem" to go into an infinite loop displaying NDFC memory addresses. Signed-off-by: NValentine Barshak <vbarshak@ru.mvista.com> Acked-by: NStefan Roese <sr@denx.de> Acked-by: NSean MacLennan <smaclennan@pikatech.com> Signed-off-by: NJosh Boyer <jwboyer@linux.vnet.ibm.com>
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由 Imre Kaloz 提交于
Add support for the NOR flash found on the AMCC Taishan Board and enable MTD support in the defconfig. Signed-off-by: NImre Kaloz <kaloz@openwrt.org> Acked-by: NStefan Roese <sr@denx.de> Signed-off-by: NJosh Boyer <jwboyer@linux.vnet.ibm.com>
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由 Josh Boyer 提交于
This reverts commit acb0142b. AMCC has indicated that the PPC 460GT does have FPU support. This revert enables the FPU for those chips again. Signed-off-by: NJosh Boyer <jwboyer@linux.vnet.ibm.com>
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由 Anton Vorontsov 提交于
This is very trivial patch. We're transitioning to the cpm_muram_* calls. That's it. Less trivial changes: - BD_SC_* defines were defined in the cpm.h and qe.h, so to avoid redefines we remove BD_SC from the qe.h and use cpm.h along with cpm_muram_* prototypes; - qe_muram_dump was unused and thus removed; - added some code to the cpm_common.c to support legacy QE bindings (data-only node name). - For convenience, define qe_* calls to cpm_*. So drivers need not to be changed. Signed-off-by: NAnton Vorontsov <avorontsov@ru.mvista.com> Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
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由 Anton Vorontsov 提交于
This is patch adds board file, device tree, and defconfig for the new board, made by Freescale Semiconductor Inc. and Logic Product Development. Currently supported: 1. UEC{1,2,7,4}; 2. I2C; 3. SPI; 4. NS16550 serial; 5. PCI and miniPCI; 6. Intel NOR StrataFlash X16 64Mbit PC28F640P30T85; 7. Graphics controller, Fujitsu MB86277. Not supported in this patch: 1. StMICRO NAND512W3A2BN6E, 512 Mbit (supported with FSL UPM NAND driver); 2. FHCI USB (supported with FHCI driver). 3. QE Serial UCCs (tested to not work with ucc_uart driver, reason unknown, yet); 4. ADC AD7843 (tested to work, but support via device tree depends on major SPI rework, GPIO API, etc); Signed-off-by: NAnton Vorontsov <avorontsov@ru.mvista.com> Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
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由 Anton Vorontsov 提交于
This is needed to access QE GPIOs via Linux GPIO API. Signed-off-by: NAnton Vorontsov <avorontsov@ru.mvista.com> Acked-By: NTimur Tabi <timur@freescale.com> Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
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- 10 6月, 2008 8 次提交
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由 Anton Vorontsov 提交于
- split and export __par_io_config_pin() out of par_io_config_pin(), so we could use the prefixed version with GPIO LIB API; - rename struct port_regs to qe_pio_regs, and place it into qe.h; - rename #define NUM_OF_PINS to QE_PIO_PINS, and place it into qe.h. Signed-off-by: NAnton Vorontsov <avorontsov@ru.mvista.com> Acked-By: NTimur Tabi <timur@freescale.com> Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
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由 Anton Vorontsov 提交于
This patch adds a function to the qe_lib to setup QE USB clocks routing. To setup clocks safely, cmxgcr register needs locking, so I just reused ucc_lock since it was used only to protect cmxgcr. The idea behind placing clocks routing functions into the qe_lib is that later we'll hopefully switch to the generic Linux Clock API, thus, for example, FHCI driver may be used for QE and CPM chips without nasty #ifdefs. This patch also fixes QE_USB_RESTART_TX command definition in the qe.h. Signed-off-by: NAnton Vorontsov <avorontsov@ru.mvista.com> Acked-By: NTimur Tabi <timur@freescale.com> Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
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由 Anton Vorontsov 提交于
GTM stands for General-purpose Timers Module and able to generate timer{1,2,3,4} interrupts. These timers are used by the drivers that need time precise interrupts (like for USB transactions scheduling for the Freescale USB Host controller as found in some QE and CPM chips), or these timers could be used as wakeup events from the CPU deep-sleep mode. Things unimplemented: 1. Cascaded (32 bit) timers (1-2, 3-4). This is straightforward to implement when needed, two timers should be marked as "requested" and configured as appropriate. 2. Super-cascaded (64 bit) timers (1-2-3-4). This is also straightforward to implement when needed, all timers should be marked as "requested" and configured as appropriate. Signed-off-by: NAnton Vorontsov <avorontsov@ru.mvista.com> Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
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由 Wolfgang Grandegger 提交于
This patch adds local bus nodes for Flash and CAN to the DTS file of the TQM8560 module (tqm8560.dts). Signed-off-by: NWolfgang Grandegger <wg@grandegger.com> Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
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由 Wolfgang Grandegger 提交于
Some TQM85xx boards could be equipped with up to 1 GiB (NOR) flash memory and therefore a modified memory map is required and setup by the board loader. This patch adds an appropriate DTS file. Signed-off-by: NWolfgang Grandegger <wg@grandegger.com> Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
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由 Wolfgang Grandegger 提交于
This patch adds support for the TQM8548 modules from TQ-Components GmbH (http://www.tqc.de). Signed-off-by: NWolfgang Grandegger <wg@grandegger.com> Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
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由 Wolfgang Grandegger 提交于
Like for the TQM5200, the vendor prefix "tqc," is now used for all TQM85xx modules from TQ-Components GmbH (http://www.tqc.de) in the corresponding DTS files. Signed-off-by: NWolfgang Grandegger <wg@grandegger.com> Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
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由 Paul Mackerras 提交于
All the maintained platforms are now in arch/powerpc, so the old arch/ppc stuff can now go away. Acked-by: NAdrian Bunk <bunk@kernel.org> Acked-by: NArnd Bergmann <arnd@arndb.de> Acked-by: NBecky Bruce <becky.bruce@freescale.com> Acked-by: NBenjamin Herrenschmidt <benh@kernel.crashing.org> Acked-by: NGeert Uytterhoeven <geert@linux-m68k.org> Acked-by: NGrant Likely <grant.likely@secretlab.ca> Acked-by: NJochen Friedrich <jochen@scram.de> Acked-by: NJohn Linn <john.linn@xilinx.com> Acked-by: NJon Loeliger <jdl@freescale.com> Acked-by: NJosh Boyer <jwboyer@linux.vnet.ibm.com> Acked-by: NKumar Gala <galak@kernel.crashing.org> Acked-by: NOlof Johansson <olof@lixom.net> Acked-by: NPeter Korsgaard <jacmet@sunsite.dk> Acked-by: NScott Wood <scottwood@freescale.com> Acked-by: NSean MacLennan <smaclennan@pikatech.com> Acked-by: NSegher Boessenkool <segher@kernel.crashing.org> Acked-by: NStefan Roese <sr@denx.de> Acked-by: NStephen Neuendorffer <stephen.neuendorffer@xilinx.com> Acked-by: NWolfgang Denk <wd@denx.de> Signed-off-by: NPaul Mackerras <paulus@samba.org>
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- 09 6月, 2008 7 次提交
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由 Trent Piepho 提交于
Since commit 4cb3cee0 the code generated for the in_beXX() and out_beXX() mmio functions has been sub-optimal. The out_leXX() family of functions are created with the macro DEF_MMIO_OUT_LE() while the out_beXX() family are created with DEF_MMIO_OUT_BE(). In what was perhaps a bit too much macro use, both of these macros are in turn created via the macro DEF_MMIO_OUT(). For the LE versions, eventually they boil down to an asm that will look something like this: asm("sync; stwbrx %1,0,%2" : "=m" (*addr) : "r" (val), "r" (addr)); The issue is that the "stwbrx" instruction only comes in an indexed, or 'x', version, in which the address is represented by the sum of two registers (the "0,%2"). Unfortunately, gcc doesn't have a constraint for an indexed memory reference. The "m" constraint allows both indexed and offset, i.e. register plus constant, memory references and there is no "stwbr" version for offset references. "m" also allows updating addresses and there is no 'u' version of "stwbrx" like there is with "stwux". The unused first operand to the asm is just to tell gcc that *addr is an output of the asm. The address used is passed in a single register via the third asm operand, and the index register is just hard coded as 0. This means gcc is forced to put the address in a single register and can't use index addressing, e.g. if one has the data in register 9, a base address in register 3 and an index in register 4, gcc must emit code like "add 11,4,3; stwbrx 9,0,11" instead of just "stwbrx 9,4,3". This costs an extra add instruction and another register. For gcc 4.0 and older, there doesn't appear to be anything that can be done. But for 4.1 and newer, there is a 'Z' constraint. It does not allow "updating" addresses, but does allow both indexed and offset addresses. However, the only allowed constant offset is 0. We can then use the undocumented 'y' operand modifier, which causes gcc to convert "0(reg)" into the equivilient "0,reg" format that can be used with stwbrx. This brings us the to problem with the BE version. In this case, the "stw" instruction does have both indexed and non-indexed versions. The final asm ends up looking like this: asm("sync; stw%U0%X0 %1,%0" : "=m" (*addr) : "r" (val), "r" (addr)); The undocumented codes "%U0" and "%0X" will generate a 'u' if the memory reference should be an auto-updating one, and an 'x' if the memory reference is indexed, respectively. The third operand is unused, it's just there because asm the code is reused from the LE version. However, gcc does not know this, and generates unnecessary code to stick addr in a register! To use the example from the LE version, gcc will generate "add 11,4,3; stwx 9,4,3". It is able to use the indexed address "4,3" for the "stwx", but still thinks it needs to put 4+3 into register 11, which will never be used. This also ends up happening a lot for the offset addressing mode, where common code like this: out_be32(&device_registers->some_register, data); uses an instruction like "stw 9, 42(3)", where register 3 has the pointer device_registers and 42 is the offset of some_register in that structure. gcc will be forced to generate the unnecessary instruction "addi 11, 3, 42" to put the address into a single (unused) register. The in_* versions end up having these exact same problems as well. Signed-off-by: NTrent Piepho <tpiepho@freescale.com> CC: Benjamin Herrenschmidt <benh@kernel.crashing.org> CC: Andreas Schwab <schwab@suse.de> Signed-off-by: NPaul Mackerras <paulus@samba.org>
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由 Michael Ellerman 提交于
When I changed irq_alloc_host() to take an of_node (52964f87: "Add an optional device_node pointer to the irq_host"), I botched the reference counting semantics. Stephen pointed out that it's irq_alloc_host()'s business if it needs to take an additional reference to the device_node, the caller shouldn't need to care. Signed-off-by: NMichael Ellerman <michael@ellerman.id.au> Signed-off-by: NPaul Mackerras <paulus@samba.org>
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由 Michael Ellerman 提交于
If we do the call to of_address_to_resource() first, then we don't need to worry about freeing the irq_host (which the code doesn't do currently anyway). Signed-off-by: NMichael Ellerman <michael@ellerman.id.au> Signed-off-by: NPaul Mackerras <paulus@samba.org>
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由 Michael Ellerman 提交于
If we do the call to of_address_to_resource() first, then we don't need to worry about freeing the irq_host (which the code doesn't do currently anyway). Signed-off-by: NMichael Ellerman <michael@ellerman.id.au> Signed-off-by: NPaul Mackerras <paulus@samba.org>
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由 Michael Ellerman 提交于
If we do the call to irq_of_parse_and_map() first, then we don't need to worry about freeing the irq_host. Signed-off-by: NMichael Ellerman <michael@ellerman.id.au> Signed-off-by: NPaul Mackerras <paulus@samba.org>
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由 Rune Torgersen 提交于
Make sure CONFIG_TASK_SIZE does not overlap CONFIG_KERNEL_START This could happen when overriding settings to get 1GB lowmem, and would lead to userland mysteriousely hanging. This setting is only used by PPC32. Signed-off-by: NRune Torgersen <runet@innovsys.com> Acked-by: NKumar Gala <galak@kernel.crashing.org> Signed-off-by: NPaul Mackerras <paulus@samba.org>
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由 Stephen Rothwell 提交于
Signed-off-by: NStephen Rothwell <sfr@canb.auug.org.au> Acked-by: NBenjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: NPaul Mackerras <paulus@samba.org>
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