Reserved for ACPI actually means that in such case the GPIO hardware will
not update the interrupt status register (GPI_IS) even if the pin is
configured to trigger an interrupt. It will update GPI_GPE_STS instead and
does not trigger an interrupt.

Allow using such pins as GPIOs, only prevent their usage as interrupts.

We also rename function intel_pad_reserved_for_acpi() to be
intel_pad_acpi_mode() which reflects the actual meaning better.
Signed-off-by: NMika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

On Intel Broxton the GPIO hardware consists of several chips that all share
the parent interrupt. It is not possible to handle this by setting chained
handler for each chip (as they will overwrite each other).

To overcome this we need to request the interrupt using devm_request_irq()
and pass IRQF_SHARED with the flags.
Signed-off-by: NMika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

For pinctrl the "default" state is applied to pins before the driver's
probe function is called.  This is normally a sensible thing to do,
but in some cases can cause problems.  That's because the pins will
change state before the driver is given a chance to program how those
pins should behave.

As an example you might have a regulator that is controlled by a PWM
(output high = high voltage, output low = low voltage).  The firmware
might leave this pin as driven high.  If we allow the driver core to
reconfigure this pin as a PWM pin before the PWM's probe function runs
then you might end up running at too low of a voltage while we probe.

Let's introudce a new "init" state.  If this is defined we'll set
pinctrl to this state before probe and then "default" after probe
(unless the driver explicitly changed states already).

An alternative idea that was thought of was to use the pre-existing
"sleep" or "idle" states and add a boolean property that we should
start in that mode.  This was not done because the "init" state is
needed for correctness and those other states are only present (and
only transitioned in to and out of) when (optional) power management
is enabled.

Changes in v3:
- Moved declarations to pinctrl/devinfo.h
- Fixed author/SoB

Changes in v2:
- Added comment to pinctrl_init_done() as per Linus W.
Signed-off-by: NDouglas Anderson <dianders@chromium.org>
Acked-by: NGreg Kroah-Hartman <gregkh@linuxfoundation.org>
Tested-by: NCaesar Wang <wxt@rock-chips.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

While IECTRL is disabled, input signals are pulled-down internally.
If pin-muxing is set up first, glitch signals (Low to High transition)
might be input to hardware blocks.

Bad case scenario:
[1] The hardware block is already running before pinctrl is handled.
   (the reset is de-asserted by default or by a firmware, for example)
[2] The pin-muxing is set up.  The input signals to hardware block
    are pulled-down by the chip-internal biasing.
[3] The pins are input-enabled.  The signals from the board reach the
    hardware block.

Actually, one invalid character is input to the UART blocks for such
SoCs as PH1-LD4, PH1-sLD8, where UART devices start to run at the
power on reset.

To avoid such problems, pins should be input-enabled before muxing.

Fixes: 6e908892 ("pinctrl: UniPhier: add UniPhier pinctrl core support")
Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>
Reported-by: NDai Okamura <okamura.dai@socionext.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

This new compatible string, "brcm,iproc-gpio", should be used for
all new iproc-based future SoCs.
Signed-off-by: NPramod Kumar <pramodku@broadcom.com>
Reviewed-by: NRay Jui <rjui@broadcom.com>
Reviewed-by: NScott Branden <sbranden@broadcom.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

Remove gpio to pinctrl pin mapping code from driver and
address this through standard property "gpio-ranges".
Signed-off-by: NPramod Kumar <pramodku@broadcom.com>
Reviewed-by: NRay Jui <rjui@broadcom.com>
Reviewed-by: NScott Branden <sbranden@broadcom.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

If GPIO controller's pins are muxed, pin-controller subsystem
need to be intimated by defining mapping between gpio and
pinmux controller. This patch adds required properties to
define this mapping via DT.
Signed-off-by: NPramod Kumar <pramodku@broadcom.com>
Reviewed-by: NRay Jui <rjui@broadcom.com>
Reviewed-by: NScott Branden <sbranden@broadcom.com>
Acked-by: NRob Herring <robh@kernel.org>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

Merge branch 'sh-pfc-for-v4.4' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into devel

Add pinmuxing for external interrupt functionality through the
sun6i "r" pincontroller.
Signed-off-by: NHans de Goede <hdegoede@redhat.com>
Acked-by: NChen-Yu Tsai <wens@csie.org>
Acked-by: NMaxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

The r_pio gpio / pin controller has a pin_base of non 0, we need to
adjust for this before calling sunxi_pinctrl_desc_find_function_by_pin.
Signed-off-by: NHans de Goede <hdegoede@redhat.com>
Acked-by: NChen-Yu Tsai <wens@csie.org>
Acked-by: NMaxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

Since the removal of the r8a7778 legacy SoC code in commit
4baadb9e ("ARM: shmobile: r8a7778: remove obsolete setup code"),
r8a7778 is only supported in generic DT-only ARM multi-platform builds.
The driver doesn't need to match platform devices by name anymore, hence
remove the corresponding platform_device_id entry.
Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be>
Acked-by: NLaurent Pinchart <laurent.pinchart@ideasonboard.com>
Acked-by: NLinus Walleij <linus.walleij@linaro.org>

Since the removal of the r8a7779 legacy SoC code in commit
c99cd90d ("ARM: shmobile: r8a7779: Remove legacy SoC code"),
r8a7779 is only supported in generic DT-only ARM multi-platform builds.
The driver doesn't need to match platform devices by name anymore, hence
remove the corresponding platform_device_id entry.
Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be>
Acked-by: NLaurent Pinchart <laurent.pinchart@ideasonboard.com>
Acked-by: NLinus Walleij <linus.walleij@linaro.org>

This header file will be removed soon.

Copy the helper macro RCAR_GP_PIN(), which is used by the pinctrl
drivers only, to sh_pfc.h, and drop the #include.
Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be>
Acked-by: NLinus Walleij <linus.walleij@linaro.org>

This header file will be removed soon.
Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be>
Acked-by: NYoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Acked-by: NGreg Kroah-Hartman <gregkh@linuxfoundation.org>
Acked-by: NFelipe Balbi <balbi@ti.com>

The sh_pfc_soc_info.gpio_data[] array contains not only GPIO data, but
also various other pinmux-related data (functions and marks).
Every single driver already calls its local array pinmux_data[].
Hence rename the sh_pfc_soc_info member to "pinmux_data".
Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be>
Acked-by: NLinus Walleij <linus.walleij@linaro.org>
Acked-by: NLaurent Pinchart <laurent.pinchart@ideasonboard.com>

On this SoC there is no simple mapping of GP pins to pull-up register
bits, so we need a table.
Signed-off-by: NUlrich Hecht <ulrich.hecht+renesas@gmail.com>
Reviewed-by: NGeert Uytterhoeven <geert+renesas@glider.be>
Acked-by: NLaurent Pinchart <laurent.pinchart@ideasonboard.com>
Acked-by: NLinus Walleij <linus.walleij@linaro.org>
Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be>

PORT_GP_CFG_1 and PORT_GP_CFG_32 work like their non-CFG counterparts
but accept an extra argument with config flags.
Signed-off-by: NUlrich Hecht <ulrich.hecht+renesas@gmail.com>
Acked-by: NLaurent Pinchart <laurent.pinchart@ideasonboard.com>
Acked-by: NLinus Walleij <linus.walleij@linaro.org>
Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be>

Add VIN0/1 pin groups to R8A7794 PFC driver.

Sergei:  rebased, renamed, added changelog, gathered 12  VIN1 data pins into
a single pin group, added "vin1_data10" pin group, used 'union vin_data' and
VIN_DATA_PIN_GROUP() macro to describe VIN1 pins, reversed the order of  the
VIN1 pin groups, removed unneeded empty lines, fixed  VIN1 separator comment.
Signed-off-by: NKoji Matsuoka <koji.matsuoka.xm@renesas.com>
Signed-off-by: NSergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be>

R8A7790/1 PFC  drivers use almost identical  'union vin_data' and completely
identical VIN_DATA_PIN_GROUP() macro; we thus can  move them into the shared
header file...
Suggested-by: NGeert Uytterhoeven <geert@linux-m68k.org>
Signed-off-by: NSergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Acked-by: NLaurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be>

When CONFIG_PM is not set we get following compilation warnings:

 warning: ‘byt_gpio_runtime_suspend’ defined but not used [-Wunused-function]
 warning: ‘byt_gpio_runtime_resume’ defined but not used [-Wunused-function]

Fix this by guarding byt_gpio_runtime_suspend()/byt_gpio_runtime_resume()
with #ifdef CONFIG_PM.
Signed-off-by: NMika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

We get following warning when CONFIG_PM_SLEEP is not set

  warning: ‘intel_gpio_irq_init’ defined but not used [-Wunused-function]

Since the function is only called from intel_pinctrl_resume() move it
inside CONFIG_PM_SLEEP guard as well.
Signed-off-by: NMika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

The DEBUG_FS=n #defines for the dbg_show functions were missed when
renaming the driver from msm_ to pm8xxx_, causing it to break the build
when DEBUG_FS isn't enabled:

  CC [M]  drivers/pinctrl/qcom/pinctrl-ssbi-gpio.o
drivers/pinctrl/qcom/pinctrl-ssbi-gpio.c:597:14: error: ‘pm8xxx_gpio_dbg_show’ undeclared here (not in a function)
  .dbg_show = pm8xxx_gpio_dbg_show,

Fix this by renaming them correctly.

Fixes: b4c45fe9 ("pinctrl: qcom: ssbi: Family A gpio & mpp drivers")
Signed-off-by: NJonas Gorski <jogo@openwrt.org>
Reviewed-by: NBjorn Andersson <bjorn.andersson@sonymobile.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

The the pin groups and pin functions have been changed
in atlas7 step B soc. We have to update the driver
to support step B chip.

Changes:
1. add 5 jtag pins to IOC_TOP:
	"jtag_tdo", "jtag_tms","jtag_tck", "jtag_tdi", "jtag_trstn"
	these 5 pins can be mutiplex with other functions, so we
	have to conver these 5 pins in pinmux.
2. add pin groups for audio digmic, audio spdif, can transceiver
	en, can transceiver stb, i2s0, i2s1 and jtag.
3. serval pins can be located to more PADs:
	audio_uart0_urfs, audio_uart1_urfs, audio_uart2_urfs,
	audio_uart2_urxd, audio_uart2_usclk, audio_uart2_utfs,
	audio_uart2_utxd, can0_rxd, can0_txd, can1_rxd, can1_txd
	jtag_ntrst, jtag_swdiotms, jtag_tck, jtag_tdi, jtag_tdo,
	pw_cko0, pw_cko1, pw_i2s01, pw_pwm0, pw_pwm1, sd2_cdb,
	sd2_wpb, uart2_cts, uart2_rts, uart2_rxd, uart2_txd,
	uart3_cts, uart3_rts, uart3_rxd, uart3_txd, uart4_cts,
	uart4_rts, usb0_drvvbus, usb1_drvvbus.

Because of Changes#3, some functions should have more than one
pin groups. So we have to split the original pin group to serval
pin groups.

For example:
audio_uart0 has 5 pins, on STEPA, each of these 5 pins only has
one related PAD. But on STEPB, audio_uart0_urfs has 4 related
PAD.
So we place the 4 pins with one PAD into a single pin group:
	audio_uart0_basic_group.
and place urfs pin wtih different PADs to 4 different pin groups:
	audio_uart0_urfs_group0, ..., audio_uart0_urfs_group3

A full audio_uart0 pin group can be:
	pinctrl-0 = <&audio_uart0_basic_group &audio_uart0_urfs_group0>;
If audio_uart0 pin group encountered some confiction, we only have
to change the urfs group:
	pinctrl-0 = <&audio_uart0_basic_group &audio_uart0_urfs_group2>;
Signed-off-by: NWei Chen <Wei.Chen@csr.com>
Signed-off-by: NBarry Song <Baohua.Song@csr.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

The previous register layout was incorrect, many of the fields having
fewer bits than were needed to represent all their modes. The new layout
is taken from the bootloader source of a BG2CD device.
Signed-off-by: NThomas Hebb <tommyhebb@gmail.com>
Acked-by: NSebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

My family name contained an accent when I submitted the
Berlin pinctrl series in the first place. There was an
encoding issue when the series was applied. Fix this.
Signed-off-by: NAntoine Ténart <antoine.tenart@free-electrons.com>
Acked-by: NSebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
[Je me rendis tous les accents aigus]
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

Berlin pinctrl drivers depends on CONFIG_OF. This patch adds
this dependency explicitly.
Signed-off-by: NAntoine Tenart <antoine.tenart@free-electrons.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

This patch prepares to remove the pinctrl driver selection from the
mach-berlin Kconfig. To do so, bool is replaced by def_bool.
Signed-off-by: NAntoine Tenart <antoine.tenart@free-electrons.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

Add berlin4ct to existing berlin pinctrl device tree binding.
Signed-off-by: NJisheng Zhang <jszhang@marvell.com>
Acked-by: NSebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Acked-by: NAntoine Tenart <antoine.tenart@free-electrons.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

Add the pin-controller driver for Marvell Berlin BG4CT SoC, with definition
of its groups and functions. This uses the core Berlin pinctrl driver.
Signed-off-by: NJisheng Zhang <jszhang@marvell.com>
Acked-by: NSebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Acked-by: NAntoine Tenart <antoine.tenart@free-electrons.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

It is good to allow berlin pinctrl driver to build with COMPILE_TEST, so
make the it menu visible when compile-testing.
Signed-off-by: NJisheng Zhang <jszhang@marvell.com>
Acked-by: NSebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Acked-by: NAntoine Tenart <antoine.tenart@free-electrons.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

This is to prepare for the next berlin4ct support, where we won't use
simple-mfd any more.
Signed-off-by: NJisheng Zhang <jszhang@marvell.com>
Acked-by: NSebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Acked-by: NAntoine Tenart <antoine.tenart@free-electrons.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

PIN_CONFIG_INPUT_SCHMITT is defined in enum_pin_config_param,
but the corresponding DT property is missing.
Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

Currently, the dt_params array in drivers/pinctrl/pinconf-generic.c
is not sorted in the same order as the enum pin_config_param in
include/linux/pinctrl/pinconf-generic.h.

Sort enum pin_config_param, conf_items, dt_params, alphabetically
for consistency.
Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

Irq argument as been removed from irq flow handlers so use the irq
descriptor to retrieve data we need.
Signed-off-by: NLudovic Desroches <ludovic.desroches@atmel.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

Use irq_set_handler_locked() as it avoids a redundant lookup of the
irq descriptor.
Signed-off-by: NLudovic Desroches <ludovic.desroches@atmel.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

Add iomuxc-lpsr devicetree bindings documentation
Provide documentation context as well an example on
pheriperals that could use pad from either iomuxc controller
supported by iMX7D SoC
Signed-off-by: NAdrian Alonso <aalonso@freescale.com>
Acked-by: NShawn Guo <shawnguo@kernel.org>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

iMX7D has two iomuxc controllers, iomuxc controller similar as
previous iMX SoC generation and iomuxc-lpsr which provides low
power state rentetion capabilities on gpios that are part of
iomuxc-lpsr

Add iomuxc-lpsr gpio group id's
Signed-off-by: NAdrian Alonso <aalonso@freescale.com>
Acked-by: NShawn Guo <shawnguo@kernel.org>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

- Add shared input select register support
- imx7d has two iomux controllers iomuxc and iomuxc-lpsr
  which share select_input register for daisy chain settings
Signed-off-by: NAdrian Alonso <aalonso@freescale.com>
Acked-by: NShawn Guo <shawnguo@kernel.org>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

Allow mux_reg offset zero to be a valid pin_id, on imx7d
mux_conf reg offset is zero for iomuxc-lspr controller
Signed-off-by: NAdrian Alonso <aalonso@freescale.com>
Acked-by: NShawn Guo <shawnguo@kernel.org>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

Fix system chrash caused by groups whose number is smaller than the number
of groups of the last pinctl instance which is not initialized.

iMX7D supports two iomux controllers (iomuxc-lpsr and iomuxc) on probing
the second instance (iomuxc) the chrash below occurs.

Uncompressing Linux... done, booting the kernel.
[    0.000000] Booting Linux on physical CPU 0x0
[    0.000000] Linux version 4.2.0-next-20150901-00006-gebfa43c (aalonso@bluefly)
[    0.000000] CPU: ARMv7 Processor [410fc075] revision 5 (ARMv7)
[    0.000000] CPU: PIPT / VIPT nonaliasing data cache, VIPT aliasin instruction cache
[    0.000000] Machine model: Freescale i.MX7 SabreSD Board
[    0.661012] [<802a6cb0>] (strcmp) from [<802cc80c>] (imx_dt_node_to_map+0x58/0x208)
[    0.668879] [<802cc80c>] (imx_dt_node_to_map) from [<802cbe24>] (pinctrl_dt_to_map+0x174/0x2b0)
[    0.677654] [<802cbe24>] (pinctrl_dt_to_map) from [<802c8f18>] (pinctrl_get+0x100/0x424)
[    0.685878] [<802c8f18>] (pinctrl_get) from [<802c9510>] (pinctrl_register+0x26c/0x480)
[    0.694104] [<802c9510>] (pinctrl_register) from [<802ccf3c>] (imx_pinctrl_probe+0x580/0x6e8)
[    0.702706] [<802ccf3c>] (imx_pinctrl_probe) from [<80351b58>] (platform_drv_probe+0x44/0xa4)
[    0.711455] [<80351b58>] (platform_drv_probe) from [<803503ec>] (driver_probe_device+0x174/0x2b4)
[    0.720405] [<803503ec>] (driver_probe_device) from [<803505fc>] (__driver_attach+0x8c/0x90)
[    0.728982] [<803505fc>] (__driver_attach) from [<8034e930>] (bus_for_each_dev+0x6c/0xa0)
[    0.737381] [<8034e930>] (bus_for_each_dev) from [<8034fb88>] (bus_add_driver+0x148/0x1f0)
[    0.745804] [<8034fb88>] (bus_add_driver) from [<80350c00>] (driver_register+0x78/0xf8)
[    0.753880] [<80350c00>] (driver_register) from [<800097d0>] (do_one_initcall+0x8c/0x1d4)
[    0.762282] [<800097d0>] (do_one_initcall) from [<80987dac>] (kernel_init_freeable+0x144/0x1e4)
[    0.771061] [<80987dac>] (kernel_init_freeable) from [<806d9c7c>] (kernel_init+0x8/0xe8)
[    0.779285] [<806d9c7c>] (kernel_init) from [<8000f628>] (ret_from_fork+0x14/0x2c)
[    0.786981] Code: e3520000 e5e32001 1afffffb e12fff1e (e4d03001)
Signed-off-by: NRobin Gong <b38343@freescale.com>
Signed-off-by: NAdrian Alonso <aalonso@freescale.com>
Acked-by: NShawn Guo <shawnguo@kernel.org>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>