The requested gpio pin must has the func_pin_mux field set
to GPIO function by BIOS/FW in advanced. Else, the gpio pin
request would fail. This is to ensure that we do not expose
any gpio pins which shall be used for alternate functions,
for eg: wakeup pin, I/O interfaces for LPSS, etc.
Signed-off-by: NChew, Kean Ho <kean.ho.chew@intel.com>
Signed-off-by: NChew, Chiau Ee <chiau.ee.chew@intel.com>
Reviewed-by: NDarren Hart <dvhart@linux.intel.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

drive_dev3_pins in pinctrl-tegra114.c wasn't used; delete it.

pinctrl-tegra124.c had quite a few typos. Fix those.

pinctrl-tegra124.c had a few mismatches between the *_groups[] ararys
and the function lists in tegra124_groups[]. Fix those.
Signed-off-by: NStephen Warren <swarren@nvidia.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

The compatible string doesn't have an x in it. Fix it. Also
remove the "qcom" prefix from pins and functions as this binding
uses the generic pinctrl bindings for the pins and functions.
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>
Reviewed-by: NBjorn Andersson <bjorn.andersson@sonymobile.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

Signed-off-by: NGeert Uytterhoeven <geert+renesas@linux-m68k.org>
Acked-by: NLaurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

Signed-off-by: NGeert Uytterhoeven <geert+renesas@linux-m68k.org>
Acked-by: NLaurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

mvebu pinctrl changes for v3.15

 - various cleanup and refactorization
 - add drivers for the Armada 375, 380, and 385 SoCs
 - prepare dove for SoC code moving into mach-mvebu
 - DT documentation updates

Sign for-mvebu/pinctrl-3xx

Sign for-mvebu/pinctrl-cleanup

Now that we have a regmap for global registers, get rid of the last
remaining hardcoded physical addresses. While at it, also remove
DOVE_ prefix from those macros.
Signed-off-by: NSebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Acked-by: NLinus Walleij <linus.walleij@linaro.org>

Now that we have ioremapped pmu_mpp registers, get rid of hardcoded
physical addresses. While at it, also remove DOVE_ prefix from those
macros.
Signed-off-by: NSebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Acked-by: NLinus Walleij <linus.walleij@linaro.org>

Now that we have an ioremapped mpp4 register, get rid of hardcoded
physical addresses. While at it, also remove DOVE_ prefix from those
macros.
Signed-off-by: NSebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Acked-by: NLinus Walleij <linus.walleij@linaro.org>

Now that we have ioremapped mpp base registers, get rid of hardcoded
physical addresses. While at it, also remove DOVE_ prefix from those
macros.
Signed-off-by: NSebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Acked-by: NLinus Walleij <linus.walleij@linaro.org>

Dove pinctrl uses some global config registers to control pins.
This patch requests a syscon regmap for those registers. As this
changes DT to driver requirements, fallback to a self-registered
regmap with hardcoded resources, if the corresponding syscon DT
node is missing. Also, WARN about old DT binding usage to encourage
users to update their DTBs.
Signed-off-by: NSebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Acked-by: NLinus Walleij <linus.walleij@linaro.org>

Dove pinctrl also requires additional registers to control all pins.
This patch requests resources for mpp4 and pmu-mpp register ranges.
As this changes DT to driver requirements, fallback to hardcoded
resources, if the corresponding DT regs have not been set.
Also, WARN about old DT binding usage to encourage users to update
their DTBs.
Signed-off-by: NSebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Acked-by: NLinus Walleij <linus.walleij@linaro.org>

Dove pinctrl binding now requires three different reg properties. This
updates corresponding binding and example accordingly. While at it, also
document reg property as required for the other MVEBU SoC pinctrl nodes.
Signed-off-by: NSebastian Hesselbarth <sebastian.hesselbarth@gmail.com>

Marvell Dove SoC binding was not documented, yet. Add the documentation
and also describe Global Configuration register node in it.
Signed-off-by: NSebastian Hesselbarth <sebastian.hesselbarth@gmail.com>

The Marvell Armada 380/385 are new ARM SoCs from Marvell, part of the
mvebu family, but using a Cortex-A9 CPU core. In terms of pin-muxing,
it is similar to Armada 370 and XP for the register layout, only
different in the number of available pins and their
functions. Therefore, we simply use the existing
drivers/pinctrl/mvebu/ infrastructure, with no other changes that the
list of pins and corresponding functions.
Signed-off-by: NThomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: NSebastian Hesselbarth <sebastian.hesselbarth@gmail.com>

The Marvell Armada 375 is a new ARM SoC from Marvell, part of the
mvebu family, but using a Cortex-A9 CPU core. In terms of pin-muxing,
it is similar to Armada 370 and XP for the register layout, only
different in the number of available pins and their
functions. Therefore, we simply use the existing
drivers/pinctrl/mvebu/ infrastructure, with no other changes that the
list of pins and corresponding functions.
Signed-off-by: NThomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: NSebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Reviewed-by: NGregory CLEMENT <gregory.clement@free-electrons.com>

Dove has pins that can be switched between normal and pmu functions.
Rework pmu_mpp callbacks to reuse default mpp ctrl helpers.
Signed-off-by: NSebastian Hesselbarth <sebastian.hesselbarth@gmail.com>

Passing a NULL name for pin ranges will auto-generate standard names
for each pin. With common pinctrl driver now checking NULL name correctly,
consolidate mpp pins 0-15.
Signed-off-by: NSebastian Hesselbarth <sebastian.hesselbarth@gmail.com>

Now that each per-SoC pinctrl driver must implement its own get/set
functions, there is no point in keeping the MPP_REG_CTRL macro, whose
purpose was to let the core pinctrl mvebu driver use default get/set
functions. While at it also update the comment about mvebu_mpp_ctrl.
Signed-off-by: NThomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: NSebastian Hesselbarth <sebastian.hesselbarth@gmail.com>

With every SoC always providing its own get/set callbacks, we can now
remove the generic ones, remove the obsolete base address, and always
use the provided callbacks.
Signed-off-by: NSebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Tested-by: NAndrew Lunn <andrew@lunn.ch>
Tested-by: NThomas Petazzoni <thomas.petazzoni@free-electrons.com>

The way that mvebu pinctrl is designed, requesting mpp registers
in common pinctrl driver does not allow SoC specific drivers to
access this resource.

Move resource allocation in each SoC pinctrl driver and enable
already provided mpp_{set,get} callbacks.
Signed-off-by: NSebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Signed-off-by: NThomas Petazzoni <thomas.petazzoni@free-electrons.com>
Tested-by: NAndrew Lunn <andrew@lunn.ch>
Tested-by: NThomas Petazzoni <thomas.petazzoni@free-electrons.com>

We want to get rid of passing register addresses to common pinctrl
driver, so provide set/get callbacks that use generic mpp pins helper
and will be used later.
Signed-off-by: NSebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Tested-by: NThomas Petazzoni <thomas.petazzoni@free-electrons.com>

We want to get rid of passing register addresses to common pinctrl
driver, so provide set/get callbacks that use generic mpp pins helper
and will be used later.
Signed-off-by: NSebastian Hesselbarth <sebastian.hesselbarth@gmail.com>

We want to get rid of passing register addresses to common pinctrl
driver, so provide set/get callbacks that use generic mpp pins helper
and will be used later.
Signed-off-by: NSebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Tested-by: NAndrew Lunn <andrew@lunn.ch>

We want to get rid of passing register addresses to common pinctrl
driver, so provide set/get callbacks that use generic mpp pins helper
and will be used later. While at it, also make use of globally defined
MPP macros.
Signed-off-by: NSebastian Hesselbarth <sebastian.hesselbarth@gmail.com>

This adds some defines and helper functions for the common mpp reg
layout to mvebu pinctrl include.
Signed-off-by: NSebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Signed-off-by: NThomas Petazzoni <thomas.petazzoni@free-electrons.com>
Tested-by: NAndrew Lunn <andrew@lunn.ch>

The only valuable information a special callback can derive from
mvebu_mpp_ctrl passed to it, is the pin id. Instead of passing
the struct, pass the pid directly.
Signed-off-by: NSebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Tested-by: NAndrew Lunn <andrew@lunn.ch>
Tested-by: NThomas Petazzoni <thomas.petazzoni@free-electrons.com>

We treat unnamed controls as generic mvebu mpp register controls but
we identify them by not being special controls. Flip the logic and
use the name pointer as identification instead. While at it, add some
comments explaining the not so obvious treatment.
Signed-off-by: NSebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Tested-by: NAndrew Lunn <andrew@lunn.ch>
Tested-by: NThomas Petazzoni <thomas.petazzoni@free-electrons.com>

With the introduction of a global name buffer, we can now remove
the allocation and preparation of per-control name buffers.
Signed-off-by: NSebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Tested-by: NAndrew Lunn <andrew@lunn.ch>
Tested-by: NThomas Petazzoni <thomas.petazzoni@free-electrons.com>

pinctrl-mvebu allows SoCs to pass unnamed controls that will get an
auto-generated name of "mpp<PIN#>". Currently, we are allocating name
buffers on a per-control basis while looping over passed controls.
This counts the total number of unnamed controls and allocates a
global name buffer instead. The new buffer is then used while assigning
controls to pinctrl groups later.
Signed-off-by: NSebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Tested-by: NAndrew Lunn <andrew@lunn.ch>
Tested-by: NThomas Petazzoni <thomas.petazzoni@free-electrons.com>

Signed-off-by: NWolfram Sang <wsa@sang-engineering.com>
Acked-by: NLaurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

This is needed for gpiod_get_direction().
Otherwise, it returns -EINVAL.
Signed-off-by: NRichard Genoud <richard.genoud@gmail.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

Introduced in commit cded80f8 ("ARM:
shmobile: r8a7791: Add MSIOF clocks in device tree").
Signed-off-by: NGeert Uytterhoeven <geert+renesas@linux-m68k.org>
Acked-by: NLaurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

The wrong index counter was being used, causing the debug message
to show an incorrect pin name.
Signed-off-by: NMartin Fuzzey <mfuzzey@parkeon.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

The correct value for selecting the mmc0 function on port F pins is 2 not 4,
as per the data-sheet:
http://dl.linux-sunxi.org/A13/A13%20Datasheet%20-%20v1.12%20%282012-03-29%29.pdfSigned-off-by: NHans de Goede <hdegoede@redhat.com>
Acked-by: NMaxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

The data pins of some peripheral are different if connecting to different
devices in one pinmux function. In the PPI case, data pins can be used
in 8, 16 and 24 pin groups individually. Add these groups into one ppi
function.
Signed-off-by: NSonic Zhang <sonic.zhang@analog.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>