1. 19 7月, 2011 1 次提交
  2. 20 4月, 2011 1 次提交
  3. 31 3月, 2011 1 次提交
  4. 05 2月, 2011 1 次提交
    • J
      ath: Fix clearing of secondary key cache entry for TKIP · 8e546104
      Jouni Malinen 提交于
      All register writes to the key cache have to be done in pairs. However,
      the clearing of a separate MIC entry with hardware revisions that use
      combined MIC key layout did not do that with one of the registers. Add
      the matching register write to the following register to make the KEY4
      register write actually complete.
      
      This is mostly a fix for a theoretical issue since the incorrect entry
      that could potentially be left behind in the key cache would not match
      with received frames. Anyway, better make this code clean the entry
      correctly using paired register writes.
      Signed-off-by: NJouni Malinen <jouni.malinen@atheros.com>
      Signed-off-by: NJohn W. Linville <linville@tuxdriver.com>
      8e546104
  5. 14 12月, 2010 1 次提交
  6. 08 12月, 2010 2 次提交
  7. 16 11月, 2010 2 次提交
  8. 17 9月, 2010 2 次提交