1. 25 2月, 2016 4 次提交
    • D
      drm/tilcdc: adopt pinctrl support · 416a07fb
      Dave Gerlach 提交于
      Update tilcdc driver to set the state of the pins to:
      - "default on resume
      - "sleep" on suspend
      
      By optionally putting the pins into sleep state in the suspend callback
      we can accomplish two things.
      - minimize current leakage from pins and thus save power,
      - prevent the IP from driving pins output in an uncontrolled manner,
      which may happen if the power domain drops the domain regulator.
      Signed-off-by: NDave Gerlach <d-gerlach@ti.com>
      Signed-off-by: NDarren Etheridge <detheridge@ti.com>
      Signed-off-by: NJyri Sarha <jsarha@ti.com>
      Reviewed-by: NTomi Valkeinen <tomi.valkeinen@ti.com>
      416a07fb
    • T
      drm/tilcdc: verify fb pitch · 6f206e9d
      Tomi Valkeinen 提交于
      LCDC hardware does not support fb pitch that is different (i.e. larger)
      than the screen size. The driver currently does no checks for this, and
      the results of too big pitch are are flickering and lower fps.
      
      This issue easily happens when using libdrm's modetest tool with non-32
      bpp modes. As modetest always allocated 4 bytes per pixel, it implies a
      bigger pitch for 16 or 24 bpp modes.
      
      This patch adds a check to reject pitches the hardware cannot support.
      Signed-off-by: NTomi Valkeinen <tomi.valkeinen@ti.com>
      Signed-off-by: NDarren Etheridge <detheridge@ti.com>
      Signed-off-by: NJyri Sarha <jsarha@ti.com>
      6f206e9d
    • D
      drm/tilcdc: rewrite pixel clock calculation · 3d19306a
      Darren Etheridge 提交于
      Updating the tilcdc DRM driver code to calculate the LCD controller
      pixel clock more accurately. Based on a suggested implementation by
      Tomi Valkeinen.
      
      The current code does not work correctly and produces wrong results
      with many requested clock rates. It also oddly uses two different
      clocks, a display pll clock and a divider clock (child of display
      pll), instead of just using the clock coming to the lcdc.
      
      This patch removes the use of the display pll clock, and rewrites the
      code to calculate the clock rates. The idea is simply to request a
      clock rate of pixelclock*2, as the LCD controller has an internal
      divider which we set to 2.
      Signed-off-by: NDarren Etheridge <detheridge@ti.com>
      [Rewrapped description]
      Signed-off-by: NJyri Sarha <jsarha@ti.com>
      Reviewed-by: NTomi Valkeinen <tomi.valkeinen@ti.com>
      3d19306a
    • D
      Merge branch 'drm/next/du' of git://linuxtv.org/pinchartl/fbdev into drm-next · 0041ee4d
      Dave Airlie 提交于
      rcar-du updates.
      
      * 'drm/next/du' of git://linuxtv.org/pinchartl/fbdev: (281 commits)
        drm: rcar-du: Add tri-planar memory formats support
        drm: rcar-du: Add probe deferral debug messages
        drm: rcar-du: lvds: Add R-Car Gen3 support
        drm: rcar-du: lvds: Rename PLLEN bit to PLLON
        drm: rcar-du: lvds: Fix PLL frequency-related configuration
        drm: rcar-du: lvds: Avoid duplication of clock clamp code
        drm: rcar-du: Add R8A7795 device support
        drm: rcar-du: Output the DISP signal on the ODDF pin
        drm: rcar-du: Output the DISP signal on the DISP pin
        drm: rcar-du: Support up to 4 CRTCs
        drm: rcar-du: Drop LVDS double dependency on OF
        drm: rcar-du: Enable compilation on ARM64
        drm: rcar-du: Fix compile warning on 64-bit platforms
        drm: rcar-du: Expose the VSP1 compositor through KMS planes
        drm: rcar-du: Move plane allocator to rcar_du_plane.c
        drm: rcar-du: Restart the DU group when a plane source changes
        drm: rcar-du: Add VSP1 compositor support
        drm: rcar-du: Add VSP1 support to the planes allocator
        drm: rcar-du: Refactor plane setup
        drm: rcar-du: Compute plane DDCR4 register value directly
        ...
      0041ee4d
  2. 23 2月, 2016 14 次提交
  3. 20 2月, 2016 10 次提交
  4. 19 2月, 2016 12 次提交