Assume that if the oscillator is enabled (OSC32EN bit is present), the
delay has already elapsed as the bootloader probably waited for the
oscillator to settle. This could waste up to 1.2s.
Signed-off-by: NAlexandre Belloni <alexandre.belloni@free-electrons.com>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

Starting with sama5d4, the crystal oscillator is always enabled at startup
and the SCKC doesn't have an OSC32EN bit anymore.

Add support for that new controller.
Signed-off-by: NAlexandre Belloni <alexandre.belloni@free-electrons.com>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

Move all clocks related to the slow clock controller to sckc.c. This avoids
extern definitions and allows to remove sckc.h
Signed-off-by: NAlexandre Belloni <alexandre.belloni@free-electrons.com>
[sboyd@codeaurora.org: Mark some functions static]
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

Initialize the GPU clock muxes to sane inputs. Until now they have
not been changed from their default values, which means that both
GPU3D shader and GPU2D core were fed by clock inputs whose rates
exceed the maximium allowed frequency of the cores by as much as
200MHz.

This fixes a severe GPU stability issue on i.MX6DL.

Cc: stable@vger.kernel.org
Signed-off-by: NLucas Stach <l.stach@pengutronix.de>
Acked-by: NShawn Guo <shawnguo@kernel.org>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

The current clock tree only implements the minimal set of differences
between the i.MX6Q and the i.MX6DL, but that doesn't really reflect
reality.

Apply the following fixes to match the RM:
- DL has no GPU3D_SHADER_SEL/PODF, the shader domain is clocked by
  GPU3D_CORE
- GPU3D_SHADER_SEL/PODF has been repurposed as GPU2D_CORE_SEL/PODF
- GPU2D_CORE_SEL/PODF has been repurposed as MLB_SEL/PODF

Cc: stable@vger.kernel.org
Signed-off-by: NLucas Stach <l.stach@pengutronix.de>
Acked-by: NShawn Guo <shawnguo@kernel.org>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

Add clocks configuration for CSI, FIRI and IEEE1588.
Signed-off-by: NFabien Lahoudere <fabien.lahoudere@collabora.co.uk>
Acked-by: NShawn Guo <shawnguo@kernel.org>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

Add clock data arrays for all UniPhier SoCs with a binding document.
Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>
Acked-by: NRob Herring <robh@kernel.org>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

This includes UniPhier clock driver code, except SoC-specific
data arrays.
Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

This clock is present on BCM53573 devices (including BCM47189) that use
Cortex-A7. ILP is a part of PMU (Power Management Unit) multi-function
device so we use syscon (and regmap) for it.
Signed-off-by: NRafał Miłecki <rafal@milecki.pl>
Acked-by: NRob Herring <robh@kernel.org>
[sboyd@codeaurora.org: Remove 0 from clk_init_data to silence sparse]
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

Adding missing reset lines for USB 3.0 PHY.
Signed-off-by: NVivek Gautam <vivek.gautam@codeaurora.org>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

The zx296718 clock driver has a creative way of assigning the register
values for each clock, by initializing an __iomem pointer to an
offset and then later adding the base (from ioremap) on top
with a cast to u64. This fail on all 32-bit architectures during
compile testing:

drivers/clk/zte/clk-zx296718.c: In function 'top_clocks_init':
drivers/clk/zte/clk-zx296718.c:554:35: error: cast from pointer to integer of different size [-Werror=pointer-to-int-cast]
   zx296718_pll_clk[i].reg_base += (u64)reg_base;
drivers/clk/zte/clk-zx296718.c:579:29: error: cast from pointer to integer of different size [-Werror=pointer-to-int-cast]
drivers/clk/zte/clk-zx296718.c:592:31: error: cast from pointer to integer of different size [-Werror=pointer-to-int-cast]

It would be nice to avoid all the casts, but I decided to simply
shut up the warnings by changing the type from u64 to uintptr_t,
which does the right thing in practice.
Signed-off-by: NArnd Bergmann <arnd@arndb.de>
Fixes: ca023328 ("clk: zx: register ZX296718 clocks")
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

A multiplication for the size determination of a memory allocation
indicated that an array data structure should be processed.
Thus use the corresponding function "kmalloc_array".

This issue was detected by using the Coccinelle software.
Signed-off-by: NMarkus Elfring <elfring@users.sourceforge.net>
Reviewed-by: NGeert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

Use the builtin_platform_driver() macro to make the code simpler.
Signed-off-by: NWei Yongjun <weiyongjun1@huawei.com>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

The register offset for the mipi-csi clk is off by 4, a copy paste
error from the mipi-dsi clk.

Fixes: c6e6c96d ("clk: sunxi-ng: Add A31/A31s clocks")
Signed-off-by: NChen-Yu Tsai <wens@csie.org>
Acked-by: NMaxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

The PLLs have a "lock" bit in their configuration registers which
indicate if the PLL has locked on to the requested clock rate. We
check this bit in the .set_rate op. The PLL cannot lock on if it's
not running, which might be a false positive (warning).

Set the CLK_SET_RATE_UNGATE flag for all PLLs so whenever clk_set_rate
is called on them, they get enabled and the "lock" check is really
checking the PLL.

Fixes: c6e6c96d ("clk: sunxi-ng: Add A31/A31s clocks")
Signed-off-by: NChen-Yu Tsai <wens@csie.org>
Acked-by: NMaxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

The LCD controller and HDMI controller use the LCDx-CHy and HDMI clocks
to generate their dot clocks. To be able to generate a full range of
possible clock rates, the parent PLL clock rates should also be changed.

Fixes: c6e6c96d ("clk: sunxi-ng: Add A31/A31s clocks")
Signed-off-by: NChen-Yu Tsai <wens@csie.org>
Acked-by: NMaxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

This patch configures the semi-synchronous mode of the video clocks
of clkgenD2.
Signed-off-by: NOlivier Bideau <olivier.bideau@st.com>
Signed-off-by: NGabriel Fernandez <gabriel.fernandez@st.com>
Acked-by: NPeter Griffin <peter.griffin@linaro.org>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

This patch allows fine tuning of the quads FS for audio clocks
accuracy.
Signed-off-by: NOlivier Bideau <olivier.bideau@st.com>
Signed-off-by: NGabriel Fernandez <gabriel.fernandez@st.com>
Acked-by: NPeter Griffin <peter.griffin@linaro.org>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

Use an algorithm instead of a table to compute clocks for fs660c32
synthesizer.
During a video playback we need to adjust audio & video frequencies.
A table can't cover all HDMI resolutions and audio adjustment.
Signed-off-by: NGabriel Fernandez <gabriel.fernandez@st.com>
Acked-by: NPeter Griffin <peter.griffin@linaro.org>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

This patch reworks the clock binding to avoid too much detail in DT.
Now we have only compatible string per type of clock
(remark from Rob https://lkml.org/lkml/2016/5/25/492)
Signed-off-by: NGabriel Fernandez <gabriel.fernandez@st.com>
Acked-by: NPeter Griffin <peter.griffin@linaro.org>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

STiH415 and STiH416 platforms are no longer used.
these platforms will be deprecated for the next kernel.
Signed-off-by: NGabriel Fernandez <gabriel.fernandez@st.com>
Acked-by: NRob Herring <robh@kernel.org>
Acked-by: NPeter Griffin <peter.griffin@linaro.org>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

Now that we have clk_hw based provider APIs to register clks, we
can get rid of struct clk pointers in this driver, allowing us to
move closer to a clear split of consumer and provider clk APIs.
Signed-off-by: NStephen Boyd <stephen.boyd@linaro.org>
Acked-by: NAlexandre Belloni <alexandre.belloni@free-electrons.com>
Tested-by: NAlexandre Belloni <alexandre.belloni@free-electrons.com>
Acked-by: NBoris Brezillon <boris.brezillon@free-electrons.com>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

Now that we have clk_hw based provider APIs to register clks, we
can get rid of struct clk pointers while registering clks in
these drivers, allowing us to move closer to a clear split of
consumer and provider clk APIs.

Cc: Eric Anholt <eric@anholt.net>
Cc: Martin Sperl <kernel@martin.sperl.org>
Signed-off-by: NStephen Boyd <stephen.boyd@linaro.org>

Make the clocks visible options that can be selected by anyone.  This
avoids the problems of:
 1) Select is a reverse dependency and is hard for people to understand
    and can sometimes be a pain to track down
 2) Build coverage goes down because configs are hidden
 3) Code bloat

Patch suggested by Stephen Boyd
Signed-off-by: NJon Mason <jonmason@broadcom.com>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

Add X-Gene PMD clock support.

PMD clock is implemented for a single register field.
  Output rate = parent_rate * (denominator - scale) / denominator
with
  - denominator = bitmask of register field + 1
  - scale = values of register field

For example, for bitmask is 0x7, denominator will be 8 and scale
will be computed and programmed accordingly.
Signed-off-by: NHoan Tran <hotran@apm.com>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

Add APM X-Gene clock binding documentation for PMD clock.
Signed-off-by: NHoan Tran <hotran@apm.com>
Acked-by: NRob Herring <robh@kernel.org>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

* clk-zte:
  clk: zx: register ZX296718 clocks
  clk: zx: reform pll config info to ease code extension

The ZX296718 clocks are statically listed and registered. More
clock will be added later.
Signed-off-by: NJun Nie <jun.nie@linaro.org>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

Add power down bit and pll lock bit in pll config structure
to ease new SoC support.
Signed-off-by: NJun Nie <jun.nie@linaro.org>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

The ZX296718 clocks are statically listed and registered. More
clock will be added later.
Signed-off-by: NJun Nie <jun.nie@linaro.org>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

Add power down bit and pll lock bit in pll config structure
to ease new SoC support.
Signed-off-by: NJun Nie <jun.nie@linaro.org>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

A multiplication for the size determination of a memory allocation
indicated that an array data structure should be processed.
Thus use the corresponding function "kmalloc_array".

This issue was detected by using the Coccinelle software.
Signed-off-by: NMarkus Elfring <elfring@users.sourceforge.net>
Reviewed-by: NAlex Elder <elder@linaro.org>
[sboyd@codeaurora.org: Save a line]
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

This helps to decode error messages like:

	[    0.000000] i.MX clk 82: register failed with -17
Signed-off-by: NUwe Kleine-König <u.kleine-koenig@pengutronix.de>
Acked-by: NShawn Guo <shawnguo@kernel.org>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

This fixes
	[    0.000000] i.MX clk 82: register failed with -17
because the name is duplicated.
Signed-off-by: NUwe Kleine-König <u.kleine-koenig@pengutronix.de>
Fixes: 3713e3f5 ("clk: imx35: define two clocks for rtc")
Acked-by: NShawn Guo <shawnguo@kernel.org>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

The addition of many gate clocks added two entries in an array for
the same value:

drivers/clk/meson/meson8b.c:479:10: error: initialized field overwritten [-Werror=override-init]
   [CLKID_GCLK_VENCI_INT]     = &meson8b_gclk_venci_int.hw,
   [CLKID_GCLK_VENCI_INT]     = &meson8b_gclk_vencp_int.hw,

This was clearly an accident, and since all other identifiers are
listed in the order in which they are defined, I'm changing the
first one to CLKID_GCLK_VENCI_INT0, making it all consistent again.
Signed-off-by: NArnd Bergmann <arnd@arndb.de>
Fixes: e31a1900 ("meson: clk: Add support for clock gates")
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

We get 1 warning when building kernel with W=1:
drivers/clk/mmp/clk-mmp2.c:75:13: warning: no previous prototype for 'mmp2_clk_init' [-Wmissing-prototypes]

In fact, this function is declared in linux/clk/mmp.h,
so this patch add missing header dependencies.
Signed-off-by: NBaoyou Xie <baoyou.xie@linaro.org>
Acked-by: NArnd Bergmann <arnd@arndb.de>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

Merge tag 'clk-renesas-for-v4.9-tag3' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into clk-next

Pull renesas clk driver updates from Geert Uytterhoeven:

  - External crystal selection for RZ/A1,
  - CMT clocks for R-Car H3 and M3-W,
  - RAVB and Thermal clocks for R-Car M3-W.

* tag 'clk-renesas-for-v4.9-tag3' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers:
  clk: renesas: r8a7796: Add CMT clocks
  clk: renesas: r8a7795: Add CMT clocks
  clk: renesas: r8a7796: Add RAVB clock
  clk: renesas: r8a7796: Add THS/TSC clock
  clk: renesas: rz: Select EXTAL vs USB clock

Use the builtin_platform_driver() macro to make the code simpler.
Signed-off-by: NWei Yongjun <weiyongjun1@huawei.com>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

Merge tag 'sunxi-clk-for-4.9' of https://git.kernel.org/pub/scm/linux/kernel/git/mripard/linux into clk-next

Pull Allwinner clock driver changes from Maxime Ripard:

Four more SoCs converted to the new clock framework (A31, A31s, A23 and
A33).

* tag 'sunxi-clk-for-4.9' of https://git.kernel.org/pub/scm/linux/kernel/git/mripard/linux:
  clk: sunxi-ng: Add hardware dependency
  clk: sunxi-ng: Add A23 CCU
  clk: sunxi-ng: Add A33 CCU support
  clk: sunxi-ng: Add N-class clocks support
  clk: sunxi-ng: mux: Add mux table macro
  clk: sunxi-ng: div: Allow to set a maximum
  clk: sunxi-ng: div: Add kerneldoc for the _ccu_div structure
  clk: sunxi-ng: div: Add mux table macros
  clk: sunxi-ng: Add A31/A31s clocks
  clk: sunxi-ng: mux: Add clk notifier functions
  clk: sunxi-ng: mux: support fixed pre-dividers on multiple parents
  clk: sunxi-ng: mux: Add support for mux tables
  clk: sunxi-ng: mux: Rename mux macro to be consistent
  clk: sunxi-ng: nkm: Add mux to support multiple parents
  clk: sunxi-ng: mux: Increase fixed pre-divider div size

Pull samsung clk driver updates from Sylwester Nawrocki:

In addition to a few clean up and code consolidation patches this
includes:
- addition of sound subsystem related clocks for Exynos5410 SoC
  (EPLL, PDMA) and support for "samsung,exynos5410-audss-clock"
  compatible in the clk-exynos-audss driver,
- addition of DRAM controller related clocks for exynos5420,
- MAINTAINERS update adding Chanwoo Choi as the Samsung SoC
  clock drivers co-maintainer.

* tag 'clk-v4.9-samsung' of git://linuxtv.org/snawrocki/samsung:
  clk: samsung: Add support for EPLL on exynos5410
  clk: samsung: clk-exynos-audss: Whitespace and debug trace cleanup
  clk: samsung: clk-exynos-audss: Add exynos5410 compatible
  clk: samsung: clk-exynos-audss: controller variant handling rework
  clk: samsung: Use common registration function for pll2550x
  clk: samsung: exynos5410: Expose the peripheral DMA gate clocks
  clk: samsung: exynos5420: Add clocks for CMU_CDREX domain
  clk: samsung: exynos5410: Use samsung_cmu_register_one() to simplify code
  clk: samsung: exynos5260: Move struct samsung_cmu_info to init section
  MAINTAINERS: Add myself as Samsung SoC clock drivers co-maintainer
  clk: samsung: exynos5410: Add clock IDs for PDMA and EPLL clocks
  clk: samsung: Add clock IDs for the CMU_CDREX (DRAM Express Controller)