1. 14 2月, 2011 1 次提交
    • M
      drm/radeon/kms: optimize CS state checking for r100->r500 · 40b4a759
      Marek Olšák 提交于
      The colorbuffer, zbuffer, and texture states are checked only once when
      they get changed. This improves performance in the apps which emit
      lots of draw packets and few state changes.
      
      This drops performance in glxgears by a 1% or so, but glxgears is not
      a benchmark we care about.
      The time spent in the kernel when running Torcs dropped from 33% to 23%
      and the frame rate is higher, which is a good thing.
      
      r600 might need something like this as well.
      Signed-off-by: NMarek Olšák <maraeo@gmail.com>
      Signed-off-by: NDave Airlie <airlied@redhat.com>
      40b4a759
  2. 27 1月, 2011 1 次提交
  3. 24 1月, 2011 1 次提交
  4. 17 1月, 2011 1 次提交
    • A
      drm/radeon/kms: balance asic_reset functions · 25b2ec5b
      Alex Deucher 提交于
      First, we were calling mc_stop() at the top of the function
      which turns off all MC (memory controller) clients,
      then checking if the GPU is idle.  If it was idle we
      returned without re-enabling the MC clients which would
      lead to a blank screen, etc.  This patch checks if the
      GPU is idle before calling mc_stop().
      
      Second, if the reset failed, we were returning without
      re-enabling the MC clients.  This patch re-enables
      the MC clients before returning regardless of whether
      the reset was successful or not.
      Signed-off-by: NAlex Deucher <alexdeucher@gmail.com>
      Cc: Jerome Glisse <jglisse@redhat.com>
      Signed-off-by: NDave Airlie <airlied@redhat.com>
      25b2ec5b
  5. 06 1月, 2011 1 次提交
    • T
      drm/radeon: use system_wq instead of dev_priv->wq · 32c87fca
      Tejun Heo 提交于
      With cmwq, there's no reason for radeon to use a dedicated workqueue.
      Drop dev_priv->wq and use system_wq instead.
      
      Because radeon_driver_irq_uninstall_kms() may be called from
      unsleepable context, the work items can't be flushed from there.
      Instead, init and flush from radeon_irq_kms_init/fini().
      
      While at it, simplify canceling/flushing of rdev->pm.dynpm_idle_work.
      Always initialize and sync cancel instead of being unnecessarily smart
      about it.
      Signed-off-by: NTejun Heo <tj@kernel.org>
      Acked-by: NAlex Deucher <alexdeucher@gmail.com>
      Cc: dri-devel@lists.freedesktop.org
      Signed-off-by: NDave Airlie <airlied@redhat.com>
      32c87fca
  6. 26 11月, 2010 1 次提交
  7. 22 11月, 2010 2 次提交
  8. 09 11月, 2010 1 次提交
  9. 28 10月, 2010 1 次提交
  10. 26 10月, 2010 1 次提交
  11. 12 10月, 2010 1 次提交
    • J
      drm/radeon/kms: avoid corner case issue with unmappable vram V2 · c919b371
      Jerome Glisse 提交于
      We should not allocate any object into unmappable vram if we
      have no means to access them which on all GPU means having the
      CP running and on newer GPU having the blit utility working.
      
      This patch limit the vram allocation to visible vram until
      we have acceleration up and running.
      
      Note that it's more than unlikely that we run into any issue
      related to that as when acceleration is not woring userspace
      should allocate any object in vram beside front buffer which
      should fit in visible vram.
      
      V2 use real_vram_size as mc_vram_size could be bigger than
         the actual amount of vram
      
      [airlied: fixup r700_cp_stop case]
      Signed-off-by: NJerome Glisse <jglisse@redhat.com>
      Signed-off-by: NDave Airlie <airlied@redhat.com>
      c919b371
  12. 06 10月, 2010 1 次提交
    • A
      drm/radeon/kms: enable writeback (v2) · 724c80e1
      Alex Deucher 提交于
      When writeback is enabled, the GPU shadows writes to certain
      registers into a buffer in memory.  The driver can then read
      the values from the shadow rather than reading back from the
      register across the bus.  Writeback can be disabled by setting
      the no_wb module param to 1.
      
      On r6xx/r7xx/evergreen, the following registers are shadowed:
      - CP scratch registers
      - CP read pointer
      - IH write pointer
      On r1xx-rr5xx, the following registers are shadowed:
      - CP scratch registers
      - CP read pointer
      
      v2:
      - Combine wb patches for r6xx-evergreen and r1xx-r5xx
      - Writeback is disabled on AGP boards since it tends to be
      unreliable on AGP using the gart.
      - Check radeon_wb_init return values properly.
      Signed-off-by: NAlex Deucher <alexdeucher@gmail.com>
      Signed-off-by: NDave Airlie <airlied@redhat.com>
      724c80e1
  13. 13 9月, 2010 2 次提交
    • M
      drm/radeon/kms: fix the colorbuffer CS checker for r300-r500 · a41ceb1c
      Marek Olšák 提交于
      This commit fixes bogus CS rejection if it contains a sequence
      of the following operations:
      
      - Set the color buffer 0. track->cb[i].robj becomes non-NULL.
      - Render.
      - Set a larger zbuffer than the previously-set color buffer.
      - Set a larger scissor area as well.
      - Set the color channel mask to 0 to do depth-only rendering.
      - Render. --> rejected, because track->cb[i].robj remained non-NULL,
        therefore the conditional checking for the color channel mask and
        friends is not performed, and the larger scissor area causes
        the rejection.
      
      This fixes bugs:
      - https://bugs.freedesktop.org/show_bug.cgi?id=29762
      - https://bugs.freedesktop.org/show_bug.cgi?id=28869
      And maybe some others which seem to look the same.
      
      If possible, this commit should go to stable as well.
      Signed-off-by: NMarek Olšák <maraeo@gmail.com>
      Signed-off-by: NDave Airlie <airlied@redhat.com>
      a41ceb1c
    • M
      drm/radeon/kms: increase lockup detection interval to 10 sec for r100-r500 · ec00efb7
      Marek Olšák 提交于
      One subtest of mesa/demos/gltestperf takes 9 seconds to complete,
      so to prevent an unnecessary gpu reset followed by a hardlock, I am
      increasing the interval to 10 seconds after which a GPU is considered
      in a locked-up state. This is on RV530. However, with a little slower GPU,
      we would surpass the interval easily, so this is not a good fix
      for gltestperf.
      
      Nevertheless, this commit also fixes hardlocks in the applications which
      render at speed of less than 1 frame per second, where the whole frame
      consists of only one command stream. The game Tiny & Big is an example.
      This bar is now lowered to 0.1 fps.
      
      Now the question comes down to whether we should (often unsuccessfully)
      reset the GPU at all? Once we have stable enough drivers, we won't have to.
      Has the time come already?
      
      If possible, this commit should go to stable as well.
      Signed-off-by: NMarek Olšák <maraeo@gmail.com>
      Signed-off-by: NDave Airlie <airlied@redhat.com>
      ec00efb7
  14. 02 8月, 2010 4 次提交
  15. 22 7月, 2010 1 次提交
    • D
      drm/radeon/kms: drop taking lock around crtc lookup. · 29508eb6
      Dave Airlie 提交于
      We only add/remove crtcs at driver load, you cannot remove when
      the GPU is running a CS packet since the fd is open, when
      GPU hotplugging on radeons actually is needed all this locking
      needs a review and I've started re-working kms core locking to deal
      with this better. But for now avoid long delays in CS processing when
      hotplug detect is happening in a different thread.
      
      this fixes a regression introduced with hotplug detection.
      Signed-off-by: NDave Airlie <airlied@redhat.com>
      29508eb6
  16. 16 7月, 2010 1 次提交
    • A
      drm/radeon/kms: fix gtt MC base alignment on rs4xx/rs690/rs740 asics · 8d369bb1
      Alex Deucher 提交于
      The asics in question have the following requirements with regard to
      their gart setups:
      
      1. The GART aperture size has to be in the form of 2^X bytes, where X is from 25 to 31
      2. The GART aperture MC base has to be aligned to a boundary equal to the size of the
      aperture.
      3. The GART page table has to be aligned to the boundary equal to the size of the table.
      4. The GART page table size is: table_entry_size * (aperture_size / page_size)
      5. The GART page table has to be allocated in non-paged, non-cached, contiguous system
      memory.
      
      This patch takes care 2.  The rest should already be handled properly.
      
      This fixes a regression noticed by: Torsten Kaiser <just.for.lkml@googlemail.com>
      Tested-by: NTorsten Kaiser <just.for.lkml@googlemail.com>
      Signed-off-by: NAlex Deucher <alexdeucher@gmail.com>
      Signed-off-by: NDave Airlie <airlied@redhat.com>
      8d369bb1
  17. 01 7月, 2010 2 次提交
  18. 15 6月, 2010 1 次提交
    • D
      radeon/kms: fix powerpc/rn50 untiled behaviour. · f5c5f040
      Dave Airlie 提交于
      Installing 2.6.34 on a Power5/rn50 combo machine, X showed buggy sw rendering,
      enabling tiling in the DDX fixed it. Investigation showed that a further /16
      was needed in the untiled case on this chipset. Need further investigations
      on what other chips this could affect, possibly rv100->rv280.
      Signed-off-by: NDave Airlie <airlied@redhat.com>
      f5c5f040
  19. 08 6月, 2010 1 次提交
    • A
      drm/radeon/kms/pm: add mid profile · c9e75b21
      Alex Deucher 提交于
      This adds an additional profile, mid, to the pm profile
      code which takes the place of the old low profile.  The default
      behavior remains the same, e.g., auto profile now selects between
      mid and high profiles based on power source, however, you can now
      manually force the low profile which was previously only available
      as a dpms off state.  Enabling the low profile when the displays
      are on has been known to cause display corruption in some cases.
      Signed-off-by: NAlex Deucher <alexdeucher@gmail.com>
      Signed-off-by: NDave Airlie <airlied@redhat.com>
      c9e75b21
  20. 01 6月, 2010 1 次提交
  21. 18 5月, 2010 14 次提交