CONFIG_HOTPLUG is going away as an option so __devinitconst is no
longer needed.
Signed-off-by: NBill Pemberton <wfp5p@virginia.edu>
Cc: Stephen Warren <swarren@wwwdotorg.org>
Acked-by: NBarry Song <baohua.song@csr.com>
Acked-by: NLinus Walleij <linus.walleij@linaro.org>
Signed-off-by: NGreg Kroah-Hartman <gregkh@linuxfoundation.org>

Staticize sirfsoc_gpio_irq_map() function.
Signed-off-by: NAxel Lin <axel.lin@ingics.com>
Acked-by: NBarry Song <Baohua.Song@csr.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

The driver supports old up SiRFprimaII SoCs, this patch makes it support
the new SiRFmarco as well.
SiRFmarco, as a SMP SoC, adds new SIRFSOC_GPIO_PAD_EN_CLR registers, to
disable GPIO pad, we should write 1 to the corresponding bit in the new
CLEAR register instead of writing 0 to SIRFSOC_GPIO_PAD_EN.
Signed-off-by: NBarry Song <Baohua.Song@csr.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

The prima2 platform advertises needing no mach/gpio.h header file,
but its pinctrl driver now has a sirfsoc_gpio_set_pull function
that uses constants defined in arch/arm/mach-prima2/include/mach/gpio.h,
which fails to build.

Fortunately, the sirfsoc_gpio_set_pull is not used anywhere in the
kernel, so we can safely remove it. Any out of tree drivers using
it will have to be converted to use proper pinctrl functions to
do the same.

Without this patch, building prima2_defconfig results in:

drivers/pinctrl/pinctrl-sirf.c: In function 'sirfsoc_gpio_set_pull':
drivers/pinctrl/pinctrl-sirf.c:1331:7: error: 'SIRFSOC_GPIO_PULL_NONE' undeclared (first use in this function)
drivers/pinctrl/pinctrl-sirf.c:1331:7: note: each undeclared identifier is reported only once for each function it appears in
drivers/pinctrl/pinctrl-sirf.c:1334:7: error: 'SIRFSOC_GPIO_PULL_UP' undeclared (first use in this function)
drivers/pinctrl/pinctrl-sirf.c:1338:7: error: 'SIRFSOC_GPIO_PULL_DOWN' undeclared (first use in this function)
Signed-off-by: NArnd Bergmann <arnd@arndb.de>
Acked-by: NBarry Song <Baohua.Song@csr.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

This patch fixes the chained irq hang issue, tested by DM9000 driver using
GPIO0-3(irqnr=131) as the external IRQ on SiRFmarco:
   $ cat /proc/interrupts
               CPU0       CPU1
     32:       1608          0       GIC  sirfsoc_timer0
     33:          0       3197       GIC  sirfsoc_timer1
     50:      10207          0       GIC  sirfsoc-uart
     56:          2          0       GIC  cc0e0000.i2c
     70:         44          0       GIC  mmc0
    131:        333          0  sirf-gpio-irq  eth0
    ...
Signed-off-by: NBarry Song <Baohua.Song@csr.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

This patch initializes the optional irq_chip pointer gc in sirfsoc
pinctrl_gpio_range.
Signed-off-by: NBaohua Song <Baohua.Song@csr.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

sirfsoc_gpio_set_input() is called in those functions which have
held the spinlock, so delete the duplicated locking.
Signed-off-by: NBarry Song <Baohua.Song@csr.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

We always use pinctrl_request_gpio() to get GPIO, If we don't have these
missing pins in the pin list, gpio_request and related operations will fail
for them.
Signed-off-by: NBarry Song <Baohua.Song@csr.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

Return 0 while probing success.
Signed-off-by: NBarry Song <Baohua.Song@csr.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

This makes us possible to define pinmux mapping in board-specific DTS.
prima2.dtsi provides all possible (groups,functions) configuration, and
device in .dts select configurations from dtsi files.
Signed-off-by: NBarry Song <Baohua.Song@csr.com>
Acked-by: NLinus Walleij <linus.walleij@linaro.org>

the pointers that are allocated with devm_kzalloc will be automatically freed,
at unload time.
Signed-off-by: NDevendra Naga <develkernel412222@gmail.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

In SiRFprimaII, Each GPIO pin can be configured as input or output
independently. If a GPIO is configured as input, it can also be
enabled as an interrupt source (either edge or level triggered).

These pins must be either MUXed as GPIO or other function pads.
Signed-off-by: NYuping Luo <yuping.luo@csr.com>
Signed-off-by: NBarry Song <Baohua.Song@csr.com>
Acked-by: NLinus Walleij <linus.walleij@linaro.org>

Signed-off-by: NBarry Song <Baohua.Song@csr.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

Most of the SoC drivers implement list_groups() and list_functions()
routines for pinctrl and pinmux. These routines continue returning
zero until the selector argument is greater than total count of
available groups or functions.

This patch replaces these list_*() routines with get_*_count()
routines, which returns the number of available selection for SoC
driver. pinctrl layer will use this value to check the range it can
choose.

This patch fixes all user drivers for this change. There are other
routines in user drivers, which have checks to check validity of
selector passed to them. It is also no more required and hence
removed.

Documentation updated as well.
Acked-by: NStephen Warren <swarren@wwwdotorg.org>
Signed-off-by: NViresh Kumar <viresh.kumar@st.com>
[Folded in fix and fixed a minor merge artifact manually]
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

This patch removes maxpin member in the pin control descriptor
because we don't need this value as we enumerate a pin space
using offset.
Signed-off-by: NChanho Park <chanho61.park@samsung.com>
Signed-off-by: NKyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

For stringent order, rename the pinmux-* pin controllers to
pinctrl-* and also rename the Kconfig symbols and in-kernel
users.

Cc: Rongjun Ying <Rongjun.Ying@csr.com>
Cc: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Acked-by: NStephen Warren <swarren@nvidia.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

This patch enables mapping a base offset of gpio ranges with
a pin offset even if does'nt matched. A base of pinctrl_gpio_range
means a base offset of gpio. However, we cannot convert gpio to pin
number for sparse gpio ranges just only using a gpio base offset.
We can convert a gpio to real pin number(even if not matched) using
a new pin_base which means a base pin offset of requested gpio range.
Now, the pin control subsystem passes the pin base offset to the
pinmux driver.

For example, let's assume below two gpio ranges in the system.

static struct pinctrl_gpio_range gpio_range_a = {
    .name = "chip a",
    .id = 0,
    .base = 32,
    .pin_base = 32,
    .npins = 16,
    .gc = &chip_a;
};

static struct pinctrl_gpio_range gpio_range_b = {
    .name = "chip b",
    .id = 0,
    .base = 48,
    .pin_base = 64,
    .npins = 8,
    .gc = &chip_b;
};

We can calucalate a exact pin ranges even if doesn't matched with gpio ranges.

chip a:
    gpio-range : [32 .. 47]
    pin-range  : [32 .. 47]
chip b:
    gpio-range : [48 .. 55]
    pin-range  : [64 .. 71]
Signed-off-by: NChanho Park <chanho61.park@samsung.com>
Signed-off-by: NKyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

Signed-off-by: NBarry Song <Baohua.Song@csr.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

fix sirfsoc_get_group_pins prototype introduced in 7e570f97, we
missed to de-constify a pointer.
Signed-off-by: NJean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Acked-by: NStephen Warren <swarren@nvidia.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

A pin controller's pin definitions are used both during pinctrl_register()
and pinctrl_unregister(). The latter happens outside of __init/__devinit
time, and hence it is unsafe to mark the pin array as __refdata.
Acked-by: NBarry Song <Baohua.Song@csr.com>
Signed-off-by: NStephen Warren <swarren@nvidia.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

get_group_pins() "returns" a pointer to an array of const objects, through
a pointer parameter. Fix the prototype so what's pointed at by the returned
pointer is const, rather than the function parameter being const.

This also allows the removal of a cast in each of the two current pinmux
drivers.
Signed-off-by: NStephen Warren <swarren@nvidia.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

This creates a pin controller driver for the SiRFprinaII
pin mux portions.
Signed-off-by: NRongjun Ying <Rongjun.Ying@csr.com>
Signed-off-by: NBarry Song <Baohua.Song@csr.com>
[Fixup for changed function names and semantics in the v10 patch]
Signed-off-by: NLinus Walleij <linus.walleij@stericsson.com>