Since all SoC drivers have been moved to local suspend/resume handling,
the old code can be safely dropped.
Signed-off-by: NTomasz Figa <t.figa@samsung.com>
Acked-by: NKyungmin Park <kyungmin.park@samsung.com>
Acked-by: NHeiko Stuebner <heiko@sntech.de>
Reviewed-by: NThomas Abraham <thomas.ab@samsung.com>
Reviewed-by: NSylwester Nawrocki <s.nawrocki@samsung.com>
Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>

Since there are multiple differences in how suspend/resume of particular
Exynos SoCs must be handled, SoC driver is better place for
suspend/resume handlers and so this patch moves them.
Signed-off-by: NTomasz Figa <t.figa@samsung.com>
Acked-by: NKyungmin Park <kyungmin.park@samsung.com>
Reviewed-by: NThomas Abraham <thomas.ab@samsung.com>
Reviewed-by: NSylwester Nawrocki <s.nawrocki@samsung.com>
Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>

Since there are multiple differences in how suspend/resume of particular
Exynos SoCs must be handled, SoC driver is better place for
suspend/resume handlers and so this patch moves them.
Signed-off-by: NTomasz Figa <t.figa@samsung.com>
Acked-by: NKyungmin Park <kyungmin.park@samsung.com>
Reviewed-by: NThomas Abraham <thomas.ab@samsung.com>
Reviewed-by: NSylwester Nawrocki <s.nawrocki@samsung.com>
Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>

Since there are multiple differences in how suspend/resume of particular
Exynos SoCs must be handled, SoC driver is better place for
suspend/resume handlers and so this patch moves them.
Signed-off-by: NTomasz Figa <t.figa@samsung.com>
Acked-by: NKyungmin Park <kyungmin.park@samsung.com>
Reviewed-by: NThomas Abraham <thomas.ab@samsung.com>
Reviewed-by: NSylwester Nawrocki <s.nawrocki@samsung.com>
Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>

Since there are multiple differences in how suspend/resume of particular
Exynos SoCs must be handled, SoC driver is better place for
suspend/resume handlers and so this patch moves them.
Signed-off-by: NTomasz Figa <t.figa@samsung.com>
Acked-by: NKyungmin Park <kyungmin.park@samsung.com>
Reviewed-by: NThomas Abraham <thomas.ab@samsung.com>
Reviewed-by: NSylwester Nawrocki <s.nawrocki@samsung.com>
Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>

As suspend/resume handlers are being moved to SoC specific code, due to
differencies in suspend/resume handling of particular SoCs, to minimize
code duplication this patch provides common register save/restore
helpers that save/restore given list of registers of clock controller.
Signed-off-by: NTomasz Figa <t.figa@samsung.com>
Acked-by: NKyungmin Park <kyungmin.park@samsung.com>
Acked-by: NHeiko Stuebner <heiko@sntech.de>
Reviewed-by: NThomas Abraham <thomas.ab@samsung.com>
Reviewed-by: NSylwester Nawrocki <s.nawrocki@samsung.com>
Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>

This patch simplifies a bit clock initialization code by removing
remnants of non-DT clock initialization, such as reg_base and xom values
passed in function parameters.
Signed-off-by: NTomasz Figa <t.figa@samsung.com>
Acked-by: NKyungmin Park <kyungmin.park@samsung.com>
Reviewed-by: NThomas Abraham <thomas.ab@samsung.com>
Reviewed-by: NSylwester Nawrocki <s.nawrocki@samsung.com>
Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>

Semicolon not needed after switch statement.
Signed-off-by: NSachin Kamat <sachin.kamat@linaro.org>
Signed-off-by: NMike Turquette <mturquette@linaro.org>

The AudioSS block on Exynos 5420 has an additional clock gate for the
ADMA bus clock.
Signed-off-by: NAndrew Bresticker <abrestic@chromium.org>
Acked-by: NMike Turquette <mturquette@linaro.org>
Acked-by: NKukjin Kim <kgene.kim@samsung.com>
Signed-off-by: NTomasz Figa <t.figa@samsung.com>

There is no gate for the PCM clock input to the AudioSS block, so
the parent of sclk_pcm is div_pcm0.  Add a clock ID for it so that
we can reference it in device trees.
Signed-off-by: NAndrew Bresticker <abrestic@chromium.org>
Reviewed-by: NTomasz Figa <t.figa@samsung.com>
Acked-by: NMike Turquette <mturquette@linaro.org>
Acked-by: NKukjin Kim <kgene.kim@samsung.com>
Signed-off-by: NTomasz Figa <t.figa@samsung.com>

This allows the input clocks to the Exynos AudioSS block to be
specified via device-tree bindings.  Default names will be used
when an input clock is not given.
Signed-off-by: NAndrew Bresticker <abrestic@chromium.org>
Acked-by: NMike Turquette <mturquette@linaro.org>
Acked-by: NKukjin Kim <kgene.kim@samsung.com>
Signed-off-by: NTomasz Figa <t.figa@samsung.com>

The Exynos AudioSS clock controller will later be modified to allow
input clocks to be specified via device-tree in order to support
multiple Exynos SoCs.  This will introduce a dependency on the core
SoC clock controller being initialized first so that the AudioSS driver
can look up its input clocks, but the order in which clock providers
are probed in of_clk_init() is not guaranteed.  Since deferred probing
is not supported in of_clk_init() and the AudioSS block is not the core
controller, we can initialize it later as a platform device.
Signed-off-by: NAndrew Bresticker <abrestic@chromium.org>
Acked-by: NTomasz Figa <t.figa@samsung.com>
Reviewed-by: NSylwester Nawrocki <s.nawrocki@samsung.com>
Acked-by: NMike Turquette <mturquette@linaro.org>
Acked-by: NKukjin Kim <kgene.kim@samsung.com>
Signed-off-by: NTomasz Figa <t.figa@samsung.com>

The patch replaces private enum clock IDs in the driver with macros provided
by the DT header.
Signed-off-by: NAndrzej Hajda <a.hajda@samsung.com>
Signed-off-by: NKyungmin Park <kyungmin.park@samsung.com>
Acked-by: NMike Turquette <mturquette@linaro.org>
Acked-by: NKukjin Kim <kgene.kim@samsung.com>
Signed-off-by: NTomasz Figa <t.figa@samsung.com>

The patch replaces private enum clock IDs in the driver with macros provided
by the DT header.
Signed-off-by: NAndrzej Hajda <a.hajda@samsung.com>
Signed-off-by: NKyungmin Park <kyungmin.park@samsung.com>
Acked-by: NMike Turquette <mturquette@linaro.org>
Acked-by: NKukjin Kim <kgene.kim@samsung.com>
Signed-off-by: NTomasz Figa <t.figa@samsung.com>

The patch replaces private enum clock IDs in the driver with macros provided
by the DT header.
Signed-off-by: NAndrzej Hajda <a.hajda@samsung.com>
Signed-off-by: NKyungmin Park <kyungmin.park@samsung.com>
Acked-by: NMike Turquette <mturquette@linaro.org>
Acked-by: NKukjin Kim <kgene.kim@samsung.com>
Signed-off-by: NTomasz Figa <t.figa@samsung.com>

The patch replaces private enum clock IDs in the driver with macros provided
by the DT header.
Signed-off-by: NAndrzej Hajda <a.hajda@samsung.com>
Signed-off-by: NKyungmin Park <kyungmin.park@samsung.com>
Acked-by: NMike Turquette <mturquette@linaro.org>
Acked-by: NKukjin Kim <kgene.kim@samsung.com>
Signed-off-by: NTomasz Figa <t.figa@samsung.com>

Register the APLL rate table so that we can set the APLL rate from
the cpufreq driver.
Signed-off-by: NAndrew Bresticker <abrestic@chromium.org>
Signed-off-by: NSachin Kamat <sachin.kamat@linaro.org>
Signed-off-by: NTomasz Figa <t.figa@samsung.com>

Add CLK_SET_RATE_PARENT flag to mout_apll clock. This will let us set the
clock rate in the cpufreq driver.
Signed-off-by: NSachin Kamat <sachin.kamat@linaro.org>
Acked-by: NMike Turquette <mturquette@linaro.org>
Signed-off-by: NTomasz Figa <t.figa@samsung.com>

This patch adds mout_aclk333_sub mux clock and updates gate clocks from
MFC domain to have it as their parent as specified in SoC documentation.
Signed-off-by: NTomasz Figa <t.figa@samsung.com>
Signed-off-by: NKyungmin Park <kyungmin.park@samsung.com>
Tested-by: NTomasz Figa <t.figa@samsung.com>

According to SoC documentation, input 5 of mout_audio muxes is connected
to xxti (named fin_pll in the driver). This patch corrects defined
parent arrays to match SoC documentation.
Signed-off-by: NTomasz Figa <t.figa@samsung.com>
Signed-off-by: NKyungmin Park <kyungmin.park@samsung.com>
Tested-by: NTomasz Figa <t.figa@samsung.com>

This patch updates mux parent arrays with unpopulated mux inputs, as all
inputs need to be specified in parent arrays passed to
clk_register_mux(), otherwise clk_set_parent() can generate out of bound
accesses to the array.
Signed-off-by: NTomasz Figa <t.figa@samsung.com>
Signed-off-by: NKyungmin Park <kyungmin.park@samsung.com>
Tested-by: NTomasz Figa <t.figa@samsung.com>

This patch adds mux_aclk_200_disp1_sub mux clock, which according to SoC
documentation is the correct parent of DISP1 gate clocks.
Signed-off-by: NTomasz Figa <t.figa@samsung.com>
Signed-off-by: NKyungmin Park <kyungmin.park@samsung.com>
Tested-by: NTomasz Figa <t.figa@samsung.com>

This patch adds mout_aclk266_gscl_sub mux clock and adjusts definitions
of GSCL domain gate clocks to use it as their parent, as specified in
SoC documentation.
Signed-off-by: NTomasz Figa <t.figa@samsung.com>
Signed-off-by: NKyungmin Park <kyungmin.park@samsung.com>
Tested-by: NTomasz Figa <t.figa@samsung.com>

This patch renames all mux clocks to start with mout_ prefix and all div
clocks to start with div_ prefix for consistency with other clocks
already defined this way.
Signed-off-by: NTomasz Figa <t.figa@samsung.com>
Signed-off-by: NKyungmin Park <kyungmin.park@samsung.com>
Tested-by: NTomasz Figa <t.figa@samsung.com>

This patch reorders clock definitions, so they are sorted by register
addresses and bitfield shifts. When at it, blank lines are added to
separate definitions of clocks from different registers.

Overall this should make the driver more readable and reduce the number
of potential conflicts when adding new entries.
Signed-off-by: NTomasz Figa <t.figa@samsung.com>
Signed-off-by: NKyungmin Park <kyungmin.park@samsung.com>
Tested-by: NTomasz Figa <t.figa@samsung.com>

Move reg_save[] into CONFIG_PM_SLEEP dependency block as it is used only
by suspend and resume functions.

This fixes the warning on CONFIG_PM_SLEEP=n:
drivers/clk/samsung/clk-exynos-audss.c:29:22: warning: ‘reg_save’ defined but not used [-Wunused-variable]
Signed-off-by: NKrzysztof Kozlowski <k.kozlowski@samsung.com>
Acked-by: NMike Turquette <mturquette@linaro.org>
Signed-off-by: NTomasz Figa <t.figa@samsung.com>

The sysreg (system register) generates control signals for various blocks
like disp1blk, i2c, mipi, usb etc. However, it gets disabled as an unused
clock at boot-up. This can lead to failures in operation of above blocks,
because they can not be configured properly if this clock is disabled.
Signed-off-by: NAbhilash Kesavan <a.kesavan@samsung.com>
Acked-by: NMike Turquette <mturquette@linaro.org>
[t.figa: Updated patch description.]
Signed-off-by: NTomasz Figa <t.figa@samsung.com>

Adds gate clock for MDMA0 on Exynos5250 SoC. This is needed to ensure
that the clock is enabled when MDMA0 is used on systems on which
firmware gates the clockby default.
Signed-off-by: NAbhilash Kesavan <a.kesavan@samsung.com>
Acked-by: NMike Turquette <mturquette@linaro.org>
[t.figa: Updated patch description.]
Signed-off-by: NTomasz Figa <t.figa@samsung.com>

The CLK_GATE_IP_ACP register offset is incorrectly listed making
definition of g2d clock incorrect, which may lead to system failures
when trying to use G2D on systems on which firmware gates this clock
by default. Fix this and the register ordering as well.
Signed-off-by: NAbhilash Kesavan <a.kesavan@samsung.com>
Acked-by: NMike Turquette <mturquette@linaro.org>
[t.figa: Updated patch description.]
Signed-off-by: NTomasz Figa <t.figa@samsung.com>

The gate clocks for the MFC sysmmus appear to be flipped, i.e.
GATE_IP_MFC[2] gates sysmmu_mfcl and GATE_IP_MFC[1] gates sysmmu_mfcr.
Fix this so that the MFC will start up.
Signed-off-by: NAndrew Bresticker <abrestic@chromium.org>
Signed-off-by: NSachin Kamat <sachin.kamat@linaro.org>
Acked-by: NMike Turquette <mturquette@linaro.org>
Signed-off-by: NTomasz Figa <t.figa@samsung.com>

The SRC_MFC register offset was incorrect, which could cause have caused
wrong calculation of rate of sclk_mfc clock, that could in turn lead to
incorrect operation of MFC. This patch corrects it.
Signed-off-by: NSeung-Woo Kim <sw0312.kim@samsung.com>
Acked-by: NMike Turquette <mturquette@linaro.org>
[t.figa: Updated patch description]
Signed-off-by: NTomasz Figa <t.figa@samsung.com>

The clock was missing CLK_SET_RATE_PARENT flag, which caused rate
setting failures due to inability of reconfiguration of second
divider behind it.
Signed-off-by: NTomasz Figa <t.figa@samsung.com>
Acked-by: NKyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>

Fixes cpll control and lock register offset values for Exynos5420 SoC.
Signed-off-by: NChander Kashyap <chander.kashyap@linaro.org>
Acked-by: NKukjin Kim <kgene.kim@samsung.com>
Signed-off-by: NMike Turquette <mturquette@linaro.org>

Since the old DMA driver got removed, these aliases are no longer
necessary.
Signed-off-by: NTomasz Figa <tomasz.figa@gmail.com>
Signed-off-by: NMark Brown <broonie@linaro.org>

This patch adds clkdev aliases for clocks used by PL08x DMA driver.
Signed-off-by: NTomasz Figa <tomasz.figa@gmail.com>
Signed-off-by: NMark Brown <broonie@linaro.org>

This patch migrates the s3c64xx platform to use the new clock driver
using Common Clock Framework.
Signed-off-by: NTomasz Figa <tomasz.figa@gmail.com>
Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>

Since the _get_rate() helper has been modified to use __clk_lookup()
internally, checking of PLL input rates can be done using it and so the
registration code can be simplified.
Signed-off-by: NTomasz Figa <t.figa@samsung.com>
Signed-off-by: NKyungmin Park <kyungmin.park@samsung.com>
Reviewed-by: NSylwester Nawrocki <s.nawrocki@samsung.com>
Signed-off-by: NMike Turquette <mturquette@linaro.org>

This patch adds rate tables for PLLs that can be reconfigured at runtime
for Exynos4x12 SoCs. Provided tables contain PLL coefficients for
input clock of 24 MHz and so are registered only in this case. MPLL does
not need runtime reconfiguration and so table for it is not provided.
Signed-off-by: NTomasz Figa <t.figa@samsung.com>
Signed-off-by: NKyungmin Park <kyungmin.park@samsung.com>
Reviewed-by: NSylwester Nawrocki <s.nawrocki@samsung.com>
Signed-off-by: NMike Turquette <mturquette@linaro.org>

This patch adds rate tables for PLLs that can be reconfigured at runtime
for Exynos4210 SoCs. Provided tables contain PLL coefficients for
input clock of 24 MHz and so are registered only in this case. MPLL does
not need runtime reconfiguration and so table for it is not provided.
Signed-off-by: NTomasz Figa <t.figa@samsung.com>
Signed-off-by: NKyungmin Park <kyungmin.park@samsung.com>
Reviewed-by: NSylwester Nawrocki <s.nawrocki@samsung.com>
Signed-off-by: NMike Turquette <mturquette@linaro.org>

Since PLL input frequency must be known before PLL registration,
mout_vpllsrc clock which is a reference clock of VPLL must be registered
before VPLL.

This patch reorders clock registration to register mout_vpllsrc before
VPLL.
Signed-off-by: NTomasz Figa <t.figa@samsung.com>
Signed-off-by: NKyungmin Park <kyungmin.park@samsung.com>
Reviewed-by: NSylwester Nawrocki <s.nawrocki@samsung.com>
Signed-off-by: NMike Turquette <mturquette@linaro.org>