- 05 4月, 2013 19 次提交
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由 Stephen Warren 提交于
Audio-related clocks need to be represented in the device tree. Update bindings to describe which clocks are needed, and DT files to include those clocks. Signed-off-by: NStephen Warren <swarren@nvidia.com>
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由 Stephen Warren 提交于
Audio-related clocks need to be represented in the device tree. Update bindings to describe which clocks are needed, and DT files to include those clocks. Signed-off-by: NStephen Warren <swarren@nvidia.com>
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由 Laxman Dewangan 提交于
NVIDIA's Tegra114 reference platform Dalmore has voltage switch regulators which are controlled by the Tegra GPIOs. Add DT node for fixed regulators. Signed-off-by: NLaxman Dewangan <ldewangan@nvidia.com> Signed-off-by: NStephen Warren <swarren@nvidia.com>
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由 Laxman Dewangan 提交于
NVIDIA's Tegra114 reference platform, Dalmore, uses the TPS65090 as secondary PMICs which is mainly act as voltage switch regulator controlled by i2c communication. Add DT node for TPS65090. Signed-off-by: NLaxman Dewangan <ldewangan@nvidia.com> [swarren: remove unit-address from node name since it's unique already] Signed-off-by: NStephen Warren <swarren@nvidia.com>
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由 Laxman Dewangan 提交于
Dalmore uses the TPS51632 as CPU regulator. The device is connected on I2C5. Add DT node for TPS51632. Signed-off-by: NLaxman Dewangan <ldewangan@nvidia.com> Signed-off-by: NStephen Warren <swarren@nvidia.com>
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由 Rhyland Klein 提交于
This patch adds the node for the bq20z45 I2C gas gauge which is compatible with the sbs-battery power supply driver. Signed-off-by: NRhyland Klein <rklein@nvidia.com> [swarren: remove unit-address from node name since it's unique already] Signed-off-by: NStephen Warren <swarren@nvidia.com>
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由 Laxman Dewangan 提交于
NVIDIA's Tegra114 has 6 SPI controllers. These controllers are redesign on T114 with different register interface. Add DT entry for spi controllers and make it compatible with "nvidia,tegra114-spi", since they are a new incompatible design. Signed-off-by: NLaxman Dewangan <ldewangan@nvidia.com> [swarren: fixed reg property for 3rd SPI controller] Signed-off-by: NStephen Warren <swarren@nvidia.com>
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由 Laxman Dewangan 提交于
NVIDIA's Tegra114 SoCs have the matrix keyboard controller which supports 11x8 type of matrix. The number of rows and columns are configurable. Add DT entry for KBC controller with compatibility as "nvidia,tegra114-kbc". Signed-off-by: NLaxman Dewangan <ldewangan@nvidia.com> Signed-off-by: NStephen Warren <swarren@nvidia.com>
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由 Laxman Dewangan 提交于
Add APB DMA requestor and serial aliases for serial controller. There are two serial drivers i.e. 8250 based simple serial driver and APB DMA based serial driver for higher baudrate and performace. The simple serial driver is selected by compatible value "nvidia,tegra114-uart", "nvidia,tegra20-uart", and the APB DMA based driver is selected by compatible value "nvidia,tegra114-hsuart", "nvidia,tegra30-hsuart". Signed-off-by: NLaxman Dewangan <ldewangan@nvidia.com> Signed-off-by: NStephen Warren <swarren@nvidia.com>
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由 Laxman Dewangan 提交于
NVIDIA's Tegra114 has 5 I2C controllers. These controllers have the following changes which makes incompatible with previous hardware: - Single clock source to I2C controller. - Interrupt support for per packet transfer. Add DT entry for I2C controllers and make it compatible with "nvidia,tegra114-i2c". Signed-off-by: NLaxman Dewangan <ldewangan@nvidia.com> [swarren: fixed location of status property for consistency] Signed-off-by: NStephen Warren <swarren@nvidia.com>
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由 Laxman Dewangan 提交于
NVIDIA's Tegra114 has 32 channels APB DMA controller. Add DT entry for APB DMA controllers and make it compatible with "nvidia,tegra114-apbdma". Tegra114 DMA controller is not compatible with Tegra30/Tegra20 DMA controller driver as in Tegra114, the global pause also clock gate the DMA register and hence it iw not possible to write the DMA register with global pause. Signed-off-by: NLaxman Dewangan <ldewangan@nvidia.com> [swarren: fixed DT node order] Signed-off-by: NStephen Warren <swarren@nvidia.com>
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由 Andrew Chew 提交于
This patch adds a device tree node for the four PWM controllers present on Tegra114. Signed-off-by: NAndrew Chew <achew@nvidia.com> Signed-off-by: NStephen Warren <swarren@nvidia.com>
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由 Andrew Chew 提交于
We should be defining the PWM nodes with status as "disabled" in the chip-specific dtsi file, since we don't know whether specific boards will use the PWM or not. This patch fixes the PWM node status for Tegra20 and Tegra30. Also fixed the one user of PWM, which is the Tegra20 medcom-wide board, so that PWM is set to "okay" in the board-specific dts file. Signed-off-by: NAndrew Chew <achew@nvidia.com> [swarren: in medcom-wide: fixed node sort order, removed duplicate pwm: label, fixed syntax error] Signed-off-by: NStephen Warren <swarren@nvidia.com>
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由 Rhyland Klein 提交于
Dalmore has a built-in eMMC device and a user-accessible SD card slot. Add device tree nodes to enable these. Based on changes by: Pritesh Raithatha <praithatha@nvidia.com> Signed-off-by: NRhyland Klein <rklein@nvidia.com> [swarren: added commit description, fixed DT node sort order] Signed-off-by: NStephen Warren <swarren@nvidia.com>
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由 Pritesh Raithatha 提交于
This patch adds in the SDHCI nodes for the busses supported on Tegra114 boards. Signed-off-by: NPritesh Raithatha <praithatha@nvidia.com> [Rhyland added clk refs to & reordered sdhci nodes and removed spaces] Signed-off-by: NRhyland Klein <rklein@nvidia.com> [swarren: fixed DT node sort order] Signed-off-by: NStephen Warren <swarren@nvidia.com>
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由 Pritesh Raithatha 提交于
This change adds the default pinctrl nodes for the Dalmore Tegra114 platform. Signed-off-by: NPritesh Raithatha <praithatha@nvidia.com> [Rhyland added patch description] Signed-off-by: NRhyland Klein <rklein@nvidia.com> Acked-by: NLinus Walleij <linus.walleij@linaro.org> [swarren: fixed DT node sort order] Signed-off-by: NStephen Warren <swarren@nvidia.com>
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由 Stephen Warren 提交于
The USB PHY nodes are all grouped together rather than being sorted based on reg address like all other nodes fix this. I apologize for the churn; I should have noticed this during review of the patches that caused this. Signed-off-by: NStephen Warren <swarren@nvidia.com>
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由 Stephen Warren 提交于
Remove white-space from empty line; triggers checkpatch. Signed-off-by: NStephen Warren <swarren@nvidia.com>
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由 Peter De Schrijver 提交于
Add references to tegra_car clocks for the basic device nodes. Also remove the clock-frequency property of the serial node as the UART driver can now use the clock framework to obtain the frequency. Signed-off-by: NPeter De Schrijver <pdeschrijver@nvidia.com> Acked-by: NMike Turquette <mturquette@linaro.org> Signed-off-by: NStephen Warren <swarren@nvidia.com>
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- 04 4月, 2013 1 次提交
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由 Joseph Lo 提交于
Adding the bindings of the clock source of PMC in DT. Signed-off-by: NJoseph Lo <josephl@nvidia.com> Signed-off-by: NStephen Warren <swarren@nvidia.com>
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- 13 3月, 2013 2 次提交
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由 Richard Genoud 提交于
There was only chip enable and readdy/busy pins for the nand controller. This add the rest of the pins. pinctrl_nand_16bits contains the specific muxes for 16 bits NANDs. Signed-off-by: NRichard Genoud <richard.genoud@gmail.com> Acked-by: NJean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> Signed-off-by: NNicolas Ferre <nicolas.ferre@atmel.com>
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由 Richard Genoud 提交于
Comments on NAND pins where inverted. Signed-off-by: NRichard Genoud <richard.genoud@gmail.com> Acked-by: NJean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> Signed-off-by: NNicolas Ferre <nicolas.ferre@atmel.com>
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- 12 3月, 2013 5 次提交
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由 Arnd Bergmann 提交于
The ab8500 device is a child of the prcmu device, which is a memory mapped bus device, whose children are addressable using physical memory addresses, not using mailboxes, so a mailbox number in the ab8500 node cannot be parsed by DT. Nothing uses this number, since it was only introduced as part of the failed attempt to clean up prcmu mailbox handling, and we can simply remove it. Signed-off-by: NArnd Bergmann <arnd@arndb.de> Signed-off-by: NSamuel Ortiz <sameo@linux.intel.com>
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由 Padmavathi Venna 提交于
This patch adds #dma-cells property to PL330 DMA controller nodes for supporting generic dma dt bindings on SOCFPGA platform. #dma-channels and #dma-requests are not required now but added in advance. Signed-off-by: NPadmavathi Venna <padma.v@samsung.com> Signed-off-by: NArnd Bergmann <arnd@arndb.de>
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由 Joseph Lo 提交于
The PMC HW is not 100% compatible across all Tegra series. We need to specify them in DT. Signed-off-by: NJoseph Lo <josephl@nvidia.com> Signed-off-by: NStephen Warren <swarren@nvidia.com>
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由 Peter De Schrijver 提交于
The new clockframework introduced DT IDs for each clock. To be able to remove the device registrations, this driver needs to be updated to use the DT IDs. Note that the actual removal of the clk_register_clkdev() calls will be done in a later series. Signed-off-by: NPeter De Schrijver <pdeschrijver@nvidia.com> Signed-off-by: NStephen Warren <swarren@nvidia.com>
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由 Joseph Lo 提交于
The GPIO pin of SD slot card detection should active low. Signed-off-by: NJoseph Lo <josephl@nvidia.com> Tested-by: NThierry Reding <thierry.reding@avionic-design.de> Signed-off-by: NStephen Warren <swarren@nvidia.com>
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- 09 3月, 2013 8 次提交
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由 Thomas Petazzoni 提交于
The orion5x-lacie-ethernet-disk-mini-v2.dts file was using "marvell-orion5x-88f5182" as a compatible string, while it should have been "marvell,orion5x-88f5182". Signed-off-by: NThomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: NJason Cooper <jason@lakedaemon.net>
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由 Thomas Petazzoni 提交于
There is no need to have a #address-cells property in the MPIC Device Tree node, and more than that, having it confuses the of_irq_map_raw() logic, which will be used by the Marvell PCIe driver. Signed-off-by: NThomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: NJason Cooper <jason@lakedaemon.net>
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由 Heikki Krogerus 提交于
Setting the reg-io-width to 1 byte represents more accurate description of the HW. This will fix an issue where UART driver causes kernel panic during bootup. Gregory CLEMENT traced the issue to autoconfig() in 8250.c, where the existence of FIFO is checked from UART_IIR register. The register is now read as 32-bit value as the reg-io-width is set to 4-bytes. The retuned value seems to contain bogus data for bits 31:8, causing the issue. Signed-off-by: NHeikki Krogerus <heikki.krogerus@linux.intel.com> Cc: Gregory CLEMENT <gregory.clement@free-electrons.com> Cc: Masami Hiramatsu <masami.hiramatsu.pt@hitachi.com> Tested-by: NGregory CLEMENT <gregory.clement@free-electrons.com> Acked-by: NGregory CLEMENT <gregory.clement@free-electrons.com> Tested-by: NMasami Hiramatsu <masami.hiramatsu.pt@hitachi.com> Tested-by: NThomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: NJason Cooper <jason@lakedaemon.net>
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由 Jean-Francois Moine 提交于
The commit: 48be9ac9 ARM: Dove: split legacy and DT setup removed the RTC initialization. This patch re-enables the RTC via the DT. Signed-off-by: NJean-François Moine <moinejf@free.fr> Signed-off-by: NJason Cooper <jason@lakedaemon.net>
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由 Florian Fainelli 提交于
This patch modifies the Armada 370 Reference Design DTS file to enable support for the two USB ports found on this board. Signed-off-by: NFlorian Fainelli <florian@openwrt.org> Signed-off-by: NJason Cooper <jason@lakedaemon.net>
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由 Andrew Lunn 提交于
The Marvell RTC on Kirkwood makes use of the runit clock. Ensure the driver clk_prepare_enable() this clock, otherwise there is a danger the SoC will lockup when accessing RTC registers with the clock disabled. Reported-by: NSimon Baatz <gmbnomis@gmail.com> Signed-off-by: NAndrew Lunn <andrew@lunn.ch> Tested-by: NSimon Baatz <gmbnomis@gmail.com> Cc: <stable@vger.kernel.org> Signed-off-by: NJason Cooper <jason@lakedaemon.net>
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由 Andrew Lunn 提交于
The kirkwood SoC GPIO cores use the runit clock. Add code to clk_prepare_enable() runit, otherwise there is a danger of locking up the SoC by accessing the GPIO registers when runit clock is not ticking. Reported-by: NSimon Baatz <gmbnomis@gmail.com> Signed-off-by: NAndrew Lunn <andrew@lunn.ch> Tested-by: NSimon Baatz <gmbnomis@gmail.com> Acked-by: NLinus Walleij <linus.walleij@linaro.org> Cc: <stable@vger.kernel.org> Signed-off-by: NJason Cooper <jason@lakedaemon.net>
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由 Jason Cooper 提交于
When DT support for kirkwood was first introduced, there was no clock infrastructure. As a result, we had to manually pass the clock-frequency to the driver from the device node. Unfortunately, on kirkwood, with minimal config or all module configs, clock-frequency breaks booting because of_serial doesn't consume the gate_clk when clock-frequency is defined. The end result on kirkwood is that runit gets gated, and then the boot fails when the kernel tries to write to the serial port. Fix the issue by removing the clock-frequency parameter from all kirkwood dts files. Booted on dreamplug without earlyprintk and successfully logged in via ttyS0. Reported-by: NSimon Baatz <gmbnomis@gmail.com> Tested-by: NSimon Baatz <gmbnomis@gmail.com> Cc: <stable@vger.kernel.org> Signed-off-by: NJason Cooper <jason@lakedaemon.net>
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- 07 3月, 2013 2 次提交
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由 Padmavathi Venna 提交于
This patch adds #dma-cells property to PL330 DMA controller nodes for supporting generic dma dt bindings on samsung exynos platforms. #dma-channels and #dma-requests are not required now but added in advance. Signed-off-by: NPadmavathi Venna <padma.v@samsung.com> Acked-by: NArnd Bergmann <arnd@arndb.de> Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>
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由 Jonathan Austin 提交于
Before jumping to (position independent) C-code from the decompressor's assembler world we set-up the C environment. This setup currently does not set r9, which for arm-none-uclinux-uclibceabi toolchains is by default expected to be the PIC offset base register (IE should point to the beginning of the GOT). Currently, therefore, in order to build working kernels that use the decompressor it is necessary to use an arm-linux-gnueabi toolchain, or similar. uClinux toolchains cause a prefetch abort to occur at the beginning of the decompress_kernel function. This patch allows uClinux toolchains to build bootable zImages by forcing the -mno-single-pic-base option, which ensures that the location of the GOT is re-derived each time it is required, and r9 becomes free for use as a general purpose register. This has a small (4% in instruction terms) advantage over the alternative of setting r9 to point to the GOT before calling into the C-world. Signed-off-by: NJonathan Austin <jonathan.austin@arm.com> Acked-by: NNicolas Pitre <nico@linaro.org> Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
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- 05 3月, 2013 3 次提交
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由 Prashant Gaikwad 提交于
As DT support for clocks and smp_twd is enabled, add clock entry for smp_twd clock to DT. This fixes the following error while booting the kernel: smp_twd: clock not found -2 Signed-off-by: NPrashant Gaikwad <pgaikwad@nvidia.com> [swarren: include kernel log spew that this fixes] Signed-off-by: NStephen Warren <swarren@nvidia.com> Signed-off-by: NOlof Johansson <olof@lixom.net>
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由 Nishanth Menon 提交于
commit 5f300acd (ARM: 7152/1: distclean: Remove generated .dtb files) ensured that dtbs were cleaned up when they were in arch/arm/boot. However, with the following commit: commit 499cd829 (ARM: dt: change .dtb build rules to build in dts directory) make clean now leaves dtbs in arch/arm/boot/dts/ untouched. Include dts directory so that clean-files rule from arch/arm/boot/dts/Makefile is invoked when make clean is done. Cc: Dirk Behme <dirk.behme@de.bosch.com> CC: Grant Likely <grant.likely@secretlab.ca> Signed-off-by: NNishanth Menon <nm@ti.com> Signed-off-by: NOlof Johansson <olof@lixom.net>
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由 Stephen Warren 提交于
BCM2835-ARM-Peripherals.pdf states that the I2C module's input clock is nominally 150MHz, and that value is currently reflected in bcm2835.dtsi. However, practical measurements show that the rate is actually 250MHz, and this agrees with various downstream kernels. Switch the I2C clock's frequency to 250MHz so that the generated bus clock rate is accurate. Signed-off-by: NStephen Warren <swarren@wwwdotorg.org> Signed-off-by: NOlof Johansson <olof@lixom.net>
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