- 21 6月, 2009 2 次提交
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由 Russell King 提交于
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
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由 Russell King 提交于
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
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- 20 6月, 2009 12 次提交
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由 Roel Kluin 提交于
with while (i++ < MAX_CLOCK_ENABLE_WAIT); i can reach MAX_CLOCK_ENABLE_WAIT + 1 after the loop, so if (i == MAX_CLOCK_ENABLE_WAIT) that's still success. Signed-off-by: NRoel Kluin <roel.kluin@gmail.com> Signed-off-by: NPaul Walmsley <paul@pwsan.com>
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由 Paul Walmsley 提交于
Correspondence with the TI OMAP hardware team indicates that SDRC_DLLA_CTRL.FIXEDDELAY should be initialized to 0x0f. This number was apparently derived from process validation. This is only used when the SDRC DLL is unlocked (e.g., SDRC clock frequency less than 83MHz). Signed-off-by: NPaul Walmsley <paul@pwsan.com>
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由 Tero Kristo 提交于
Previously only 1 and 2 was supported. This is needed for DVFS VDD2 control. Signed-off-by: NTero Kristo <tero.kristo@nokia.com>
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由 Paul Walmsley 提交于
Convert omap3_sram_configure_core_dpll() to use macros rather than magic numbers. Signed-off-by: NPaul Walmsley <paul@pwsan.com>
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由 Paul Walmsley 提交于
Clean up comments and copyrights on the CORE DPLL3 M2 divider change code. Signed-off-by: NPaul Walmsley <paul@pwsan.com>
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由 Paul Walmsley 提交于
Program the SDRC_MR_0 register as well during SDRC clock changes. This register allows selection of the memory CAS latency. Some SDRAM chips, such as the Qimonda HYB18M512160AF6, have a lower CAS latency at lower clock rates. Signed-off-by: NPaul Walmsley <paul@pwsan.com>
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由 Paul Walmsley 提交于
When changing the SDRAM clock from 166MHz to 83MHz via the CORE DPLL M2 divider, add a short delay before returning to SDRAM to allow the SDRC time to stabilize. Without this delay, the system is prone to random panics upon re-entering SDRAM. This time delay varies based on MPU frequency. At 500MHz MPU frequency at room temperature, 64 loops seems to work okay; so add another 32 loops for environmental and process variation. Signed-off-by: NPaul Walmsley <paul@pwsan.com>
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由 Paul Walmsley 提交于
On the OMAP3, initialize SDRC timings when the kernel boots. This ensures that the kernel is running with known, optimized SDRC timings, rather than whatever was configured by the bootloader. Signed-off-by: NPaul Walmsley <paul@pwsan.com>
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由 Paul Walmsley 提交于
The original CDP kernel that this code comes from waited for 0x800 loops after switching the CORE DPLL M2 divider. This does not appear to be necessary. Signed-off-by: NPaul Walmsley <paul@pwsan.com>
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由 Joonyoung Shim 提交于
This patch supports the cache handling for some old Feroceon cores for which the CPU ID is like 0x41159260. This is a complement to commit ab6d15d5. Signed-off-by: NJoonyoung Shim <jy0922.shim@samsung.com> Signed-off-by: NNicolas Pitre <nico@marvell.com>
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- 19 6月, 2009 8 次提交
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由 Catalin Marinas 提交于
When a kthread function returns, it branches to do_exit(). However, the unwinding information isn't valid anymore and any stack trace caused by do_exit() may be incorrect. This patch adds a kernel_thread_exit() function and annotated with '.cantunwind' so that the unwinder stops when reaching it. Tested-by: NTony Lindgren <tony@atomide.com> Signed-off-by: NCatalin Marinas <catalin.marinas@arm.com> Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
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由 Catalin Marinas 提交于
There are situations where the unwinder goes beyond stack boundaries and unwinds random data. This patch moves the stack boundaries check after the unwind_exec_insn() call and adds an extra check for possible infinite loops (like "mov pc, lr" with pc == lr). The patch also fixes a bug in the unwind instructions interpreter. The 0xb0 instruction can only set PC to LR if this wasn't already set by a previous instruction (this is used on exceptions taken while in kernel mode where svc_entry is annotated with ".save {r0 - pc}"). Tested-by: NTony Lindgren <tony@atomide.com> Signed-off-by: NCatalin Marinas <catalin.marinas@arm.com> Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
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由 Catalin Marinas 提交于
Not discarding these sections when hotplug isn't available prevents the kernel from building. Signed-off-by: NCatalin Marinas <catalin.marinas@arm.com> Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
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由 George G. Davis 提交于
From: Min Zhang <mzhang@mvista.com> Add alignment fault fixup support for 32-bit Thumb-2 LDM, LDRD, POP, PUSH, STM and STRD instructions. Alignment fault fixup support for the remaining 32-bit Thumb-2 load/store instruction cases is not included since ARMv6 and later processors include hardware support for loads and stores of unaligned words and halfwords. Signed-off-by: NMin Zhang <mzhang@mvista.com> Signed-off-by: NGeorge G. Davis <gdavis@mvista.com> Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
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由 Catalin Marinas 提交于
The cpu member of struct irq_desc was recently renamed to node. The patch renames the ARM references to the old member. Signed-off-by: NCatalin Marinas <catalin.marinas@arm.com> Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
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由 Catalin Marinas 提交于
This header file is needed for twd_base. Signed-off-by: NCatalin Marinas <catalin.marinas@arm.com> Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
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由 Russell King 提交于
Merge branch 'for-rmk' of git://git.kernel.org/pub/scm/linux/kernel/git/ycmiao/pxa-linux-2.6 into devel
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- 18 6月, 2009 18 次提交
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由 Matthew Wilcox 提交于
ia64 was assigning resources to root busses after allocations had been made for child busses. Calling pcibios_setup_root_windows() from pcibios_fixup_bus() solves this problem by assigning the resources to the root bus before child busses are scanned. Signed-off-by: NMatthew Wilcox <willy@linux.intel.com> Tested-by: NAndrew Patterson <andrew.patterson@hp.com> Signed-off-by: NLinus Torvalds <torvalds@linux-foundation.org>
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由 Matthew Wilcox 提交于
Instead of open-coding pci_find_parent_resource and request_resource, just call pci_claim_resource. Signed-off-by: NMatthew Wilcox <willy@linux.intel.com> Signed-off-by: NLinus Torvalds <torvalds@linux-foundation.org>
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由 Matthew Wilcox 提交于
This function was only used by pci_claim_resource(), and the last commit deleted that use. Signed-off-by: NMatthew Wilcox <willy@linux.intel.com> Signed-off-by: NLinus Torvalds <torvalds@linux-foundation.org>
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由 Matthew Wilcox 提交于
Instead of starting from the iomem or ioport roots, start from the parent bus' resources. This fixes a bug where child resources would appear above their parents resources if they had the same size. Signed-off-by: NMatthew Wilcox <willy@linux.intel.com> Tested-by: NAndrew Patterson <andrew.patterson@hp.com> Signed-off-by: NLinus Torvalds <torvalds@linux-foundation.org>
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git://git.kernel.org/pub/scm/linux/kernel/git/aegl/linux-2.6由 Linus Torvalds 提交于
* 'release' of git://git.kernel.org/pub/scm/linux/kernel/git/aegl/linux-2.6: [IA64] Convert ia64 to use int-ll64.h [IA64] Fix build error in paravirt_patchlist.c [IA64] ia64 does not need umount2() syscall [IA64] hook up new rt_tgsigqueueinfo syscall [IA64] msi_ia64.c dmar_msi_type should be static [IA64] remove obsolete hw_interrupt_type [IA64] remove obsolete irq_desc_t typedef [IA64] remove obsolete no_irq_type [IA64] unexport fpswa.h
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git://git.kernel.org/pub/scm/linux/kernel/git/sameo/mfd-2.6由 Linus Torvalds 提交于
* 'for-next' of git://git.kernel.org/pub/scm/linux/kernel/git/sameo/mfd-2.6: mfd: early init for MFD running regulators mfd: fix tmio related warnings mfd: asic3: enable SD/SDIO cell mfd: asic3: enable DS1WM cell mfd: asic3: remove SD/SDIO controller register definitions mfd: asic3: use resource_size macro instead of local variable mfd: add ASIC3 IRQ numbers mfd: asic3: add clock handling for MFD cells mfd: asic3: add asic3_set_register common operation mfd: Fix Kconfig help text for WM8350 mfd: add PCAP driver mfd: add U300 AB3100 core support drivers/mfd: remove obsolete irq_desc_t typedef mfd/pcf50633-gpio.c: add MODULE_LICENSE mfd: Mark WM8350 mask revision as readable to match silicon mfd: Mark clocks_init as non-init in twl4030-core.c mfd: Correct readability of WM8350 register 227
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git://linux-arm.org/linux-2.6由 Linus Torvalds 提交于
* 'kmemleak' of git://linux-arm.org/linux-2.6: kmemleak: Fix some typos in comments kmemleak: Rename kmemleak_panic to kmemleak_stop kmemleak: Only use GFP_KERNEL|GFP_ATOMIC for the internal allocations
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由 Samuel Ortiz 提交于
For MFDs running regulator cores, we really want them to be brought up early during boot. Signed-off-by: NSamuel Ortiz <sameo@linux.intel.com> Acked-by: NMark Brown <broonie@opensource.wolfsonmicro.com> Acked-by: NMike Rapoport <mike@compulab.co.il>
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由 Samuel Ortiz 提交于
We can not have .driver_data as const since platform_set_drvdata() doesnt take a const. The hclk mmc_data field can be const though. Signed-off-by: NSamuel Ortiz <sameo@linux.intel.com>
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由 Philipp Zabel 提交于
This enables the ASIC3's SD/SDIO MFD cell, supported by the tmio_mmc driver. Signed-off-by: NPhilipp Zabel <philipp.zabel@gmail.com> Signed-off-by: NSamuel Ortiz <sameo@linux.intel.com>
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由 Philipp Zabel 提交于
This enables the ASIC3's DS1WM MFD cell, supported by the ds1wm driver. Signed-off-by: NPhilipp Zabel <philipp.zabel@gmail.com> Signed-off-by: NSamuel Ortiz <sameo@linux.intel.com>
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由 Philipp Zabel 提交于
Only the base addresses remain, as they are needed to set up the IOMEM resources. Signed-off-by: NPhilipp Zabel <philipp.zabel@gmail.com> Signed-off-by: NSamuel Ortiz <sameo@linux.intel.com>
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由 Philipp Zabel 提交于
This should make the code a little bit easier to read. Signed-off-by: NPhilipp Zabel <philipp.zabel@gmail.com> Signed-off-by: NSamuel Ortiz <sameo@linux.intel.com>
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由 Philipp Zabel 提交于
IRQ number definitions for PWM, LED, SPI and OWM (ds1wm). Signed-off-by: NPhilipp Zabel <philipp.zabel@gmail.com> Signed-off-by: NSamuel Ortiz <sameo@linux.intel.com>
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由 Philipp Zabel 提交于
Since ASIC3 has to work on both PXA and S3C and since their struct clk implementations differ, we can't register out clocks with the clkdev mechanism (yet?). For now we have to keep clock handling internal to this driver and enable/disable the clocks via the mfd_cell->enable/disable functions. Signed-off-by: NPhilipp Zabel <philipp.zabel@gmail.com> Signed-off-by: NSamuel Ortiz <sameo@linux.intel.com>
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由 Philipp Zabel 提交于
Used to configure single bits of the SDHWCTRL_SDCONF and EXTCF_RESET/SELECT registers needed for DS1WM, MMC/SDIO and PCMCIA functionality. Signed-off-by: NPhilipp Zabel <philipp.zabel@gmail.com> Signed-off-by: NSamuel Ortiz <sameo@linux.intel.com>
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由 Mark Brown 提交于
More with the grammar. Signed-off-by: NMark Brown <broonie@opensource.wolfsonmicro.com> Signed-off-by: NSamuel Ortiz <sameo@linux.intel.com>
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由 Daniel Ribeiro 提交于
The PCAP Asic as present on EZX phones is a multi function device with voltage regulators, ADC, touch screen controller, RTC, USB transceiver, leds controller, and audio codec. It has two SPI ports, typically one is connected to the application processor and another to the baseband, this driver provides read/write functions to its registers, irq demultiplexer and ADC queueing/abstraction. This chip is used on a lot of Motorola phones, it was manufactured by TI as a custom product with the name PTWL93017, later this design evolved into the ATLAS PMIC from Freescale (MC13783). Signed-off-by: NDaniel Ribeiro <drwyrm@gmail.com> Signed-off-by: NSamuel Ortiz <sameo@linux.intel.com>
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