Add pins, groups, and functions for MSIOF on R-Car H3 ES2.0.

Extracted from a big patch in the BSP by Takeshi Kihara, with
corrections for MSIOF3 SS1_E/SS2_E pins and SS2_E mux.
Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be>

This patch fixes the incorrect IPSR register value definitions for
MSIOF3_{SS1,SS2}_E pin functions.

This is a correction to the incorrect implementation of IPSR register pin
assignment of the specifications updated for R8A7795 ES2.0 SoC in R-Car
Gen3 Hardware User's Manual Rev.0.53E.

Fixes: b205914c ("pinctrl: sh-pfc: r8a7795: Add support for R-Car H3 ES2.0")
Signed-off-by: NTakeshi Kihara <takeshi.kihara.df@renesas.com>
[geert: Reword, update Fixes for upstream]
Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be>

Add pinctrl support for the PWM[0-6] pins.
Signed-off-by: NLaurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be>

The H3 ES1.x and H3 ES2.0 have identical pinmuxing for the parallel RGB
output support.
Signed-off-by: NLaurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be>

Add pins, groups, and a function for EtherAVB on R-Car H3 ES2.0.

Extracted from a big patch in the BSP by Takeshi Kihara.
Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be>

R-Car Gen3 is using SSI_{WS,SCK}349 instead of SSI_{WS,SCK}34.
But, current code is based on old datasheet which had typo.
This patch fixes this typo.
Signed-off-by: NKuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be>

Add pins, groups, and a function for SCIF_CLK on R-Car H3 ES2.0.
SCIF_CLK is the external clock source for the Baud Rate Generator for
External Clock (BRG) on (H)SCIF serial ports.

Extracted from a big patch in the BSP by Takeshi Kihara.
Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be>
Cc: Takeshi Kihara <takeshi.kihara.df@renesas.com>

Add pins, groups, and functions for all SCIF serial ports on R-Car H3
ES2.0.

Extracted from a big patch in the BSP by Takeshi Kihara.
Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be>
Cc: Takeshi Kihara <takeshi.kihara.df@renesas.com>

The Pin Function Controller module in the R-Car H3 ES2.0 differs from
ES1.x in many ways.

The goal is twofold:
  1. Support both the ES1.x and ES2.0 SoC revisions in a single binary
     for now,
  2. Make it clear which code supports ES1.x, so it can easily be
     identified and removed later, when production SoCs are deemed
     ubiquitous.

Hence this patch:
  1. Extracts the support for R-Car H3 ES1.x into a separate file, as
     the differences are quite large,
  2. Adds code for detecting the SoC revision at runtime using the new
     soc_device_match() API, and selecting pinctrl tables for the actual
     SoC revision,
  3. Replaces the core register and bitfield definitions by their
     counterparts for R-Car H3 ES2.0.

The addition of pins, groups, and functions for the various on-chip
devices is left to subsequent patches.

The R-Car H3 ES2.0 register and bitfield definitions were extracted from
a patch in the BSP by Takeshi Kihara.
Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be>
Cc: Takeshi Kihara <takeshi.kihara.df@renesas.com>

Somehow the QSPI and SCIF_CLK fragments were inserted at the wrong
positions.  Restore sort order (alphabetically, per group).
Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be>

Fix typos in hscif2_clk_b_mux[] and hscif4_ctrl_mux[].

Fixes: a56069c4 ("pinctrl: sh-pfc: r8a7795: Add HSCIF pins, groups, and functions")
Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be>

There are pins on the r8a7795 which are not part of a GPIO bank nor
can be muxed between different functions. They do however allow for the
bias to be configured. Add those pins to the list of pins and
to the bias configuration array.

The pins can now be referred to in DT by function names and their bias
setting set.
Signed-off-by: NNiklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be>

Group the QSPI0 and QSPI1 pins into similar groups found in other sh-pfc
drivers. The pins can not be muxed between functions other than QSPI,
but their drive strength can be controlled.
Signed-off-by: NNiklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be>

Group the AVB pins into similar groups found in other sh-pfc drivers.
The pins can not be muxed between functions other then AVB but their
drive strength can be controlled.

The group avb_mdc containing ADV_MDC and ADV_MDIO are on other SoCs
called avb_mdio. In pfc-r8a7795 the avb_mdc group already existed and
is in use in DT. Therefore add the ADV_MDIO pin to the existing group
instead of renaming it.
Signed-off-by: NNiklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be>

There are pins on the r8a7795 which are not part of a GPIO bank nor
can be muxed between different functions. They do however allow for the
drive-strength to be configured. Add those pins to the list of pins and
to the drive-strength configuration registers.

The pins can now be referred to in DT by function names and their
drive-strength modified.
Signed-off-by: NNiklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be>

There is a bug in the r8a7795 bias code where a WARN() is trigged
anytime a pin from PUEN0/PUD0 is accessed.

 # cat /sys/kernel/debug/pinctrl/e6060000.pfc/pinconf-pins

 WARNING: CPU: 2 PID: 2391 at drivers/pinctrl/sh-pfc/pfc-r8a7795.c:5364 r8a7795_pinmux_get_bias+0xbc/0xc8
 [..]
 Call trace:
 [<ffff0000083c442c>] r8a7795_pinmux_get_bias+0xbc/0xc8
 [<ffff0000083c37f4>] sh_pfc_pinconf_get+0x194/0x270
 [<ffff0000083b0768>] pin_config_get_for_pin+0x20/0x30
 [<ffff0000083b11e8>] pinconf_generic_dump_one+0x168/0x188
 [<ffff0000083b144c>] pinconf_generic_dump_pins+0x5c/0x98
 [<ffff0000083b0628>] pinconf_pins_show+0xc8/0x128
 [<ffff0000081fe3bc>] seq_read+0x16c/0x420
 [<ffff00000831a110>] full_proxy_read+0x58/0x88
 [<ffff0000081d7ad4>] __vfs_read+0x1c/0xf8
 [<ffff0000081d8874>] vfs_read+0x84/0x148
 [<ffff0000081d9d64>] SyS_read+0x44/0xa0
 [<ffff000008082f4c>] __sys_trace_return+0x0/0x4

This is due to the WARN() check if the reg field of the pullups struct
is zero, and this should be 0 for pins controlled by the PUEN0/PUD0
registers since PU0 is defined as 0. Change the data structure and use
the generic sh_pfc_pin_to_bias_info() function to get the register
offset and bit information.

Fixes: 56065524 ("pinctrl: sh-pfc: r8a7795: Add bias pinconf support")
Signed-off-by: NNiklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
Reviewed-by: NLaurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be>

The last else statement is missing braces, and the indentation level can
be reduced.
Suggested-by: NLaurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: NNiklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
Reviewed-by: NLaurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be>

Only the DU parallel RGB output signals are included, HDMI and TCON pins
will be added in separate groups.
Signed-off-by: NLaurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be>

This source file handles r8a7795 only, which is not the sole member of
the R-Car Gen3 family.
Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be>
Acked-by: NLinus Walleij <linus.walleij@linaro.org>

Implements pull-up and pull-down. On this SoC there is no simple mapping of
GP pins to bias register bits, so we need a table.
Signed-off-by: NUlrich Hecht <ulrich.hecht+renesas@gmail.com>
Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be>

This patch adds DRIF[0-3] pinmux support for r8a7795 SoC.
Signed-off-by: NRamesh Shanmugasundaram <ramesh.shanmugasundaram@bp.renesas.com>
Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be>

Now we have PINMUX_SINGLE(). Let's use it instead of PINMUX_IPSR_NOGP()
Signed-off-by: NKuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Acked-by: NLinus Walleij <linus.walleij@linaro.org>
Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be>

Signed-off-by: NWolfram Sang <wsa+renesas@sang-engineering.com>
Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be>

Define the drive strength registers for the R8A7795. As the PFC driver
for the SoC only defines GPIO pins at the moment, limit drive strength
support to those pins. Pins without GPIO capabilities will be supported
later.
Signed-off-by: NLaurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be>

This patch adds CANFD[0-1] pinmux support to r8a7795 SoC.
Signed-off-by: NRamesh Shanmugasundaram <ramesh.shanmugasundaram@bp.renesas.com>
Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be>

This patch adds CAN[0-1] pinmux support to r8a7795 SoC.
Signed-off-by: NRamesh Shanmugasundaram <ramesh.shanmugasundaram@bp.renesas.com>
Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be>

This patch adds PWM[0-6] pinmux support to r8a7795 SoC.
Signed-off-by: NTakeshi Kihara <takeshi.kihara.df@renesas.com>
[uli: adapted to mainline PFC driver]
Signed-off-by: NUlrich Hecht <ulrich.hecht+renesas@gmail.com>
Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be>

Most pins on the r8a7795 SoC can be configured in GPIO mode for
interrupt and GPIO functionality, while a couple of them can also
be routed to the INTC-EX hardware block (formerly known as IRQC).

On r8a7795 the INTC-EX hardware handles pins IRQ0 -> IRQ5 and
this patch adds support for them to the PFC driver as "intc_ex_irqN".

Tested on r8a7795 Salvator-X with an external loop back adapter on
EXIO_D that connects pin 9 (IRQ2/GP2_02) and pin 26 (ExA22/GP2_06).
Signed-off-by: NMagnus Damm <damm+renesas@opensource.se>
Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be>

This patch adds USB[0-2] (USB2.0 host) pinmux support to r8a7795 SoC.
Signed-off-by: NTakeshi Kihara <takeshi.kihara.df@renesas.com>
Signed-off-by: NYoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be>

Cfr. Manual Errata for Rev 0.50 of the R-Car Gen3 datasheet.

This has no user-visible impact, as the definitions were not really
used.
Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be>
Acked-by: NLinus Walleij <linus.walleij@linaro.org>

Cfr. Manual Errata for Rev 0.50 of the R-Car Gen3 datasheet.

This has no user-visible impact, as the string used for configuration
("ssi01239_ctrl") was already correct.
Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be>
Acked-by: NLinus Walleij <linus.walleij@linaro.org>

This macro describes a pinmux configuration that needs configuration in
both a Peripheral Function Select Register (IPSR) and in a
GPIO/Peripheral Function Select Register 1 (GPSR). Reflect that in the
macro name for clarity.
Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be>
Acked-by: NLaurent Pinchart <laurent.pinchart@ideasonboard.com>

This patch adds SATA0 pinmux support to r8a7795 SoC.
Signed-off-by: NTakeshi Kihara <takeshi.kihara.df@renesas.com>
[uli: adjusted for new PFC driver]
Signed-off-by: NUlrich Hecht <ulrich.hecht+renesas@gmail.com>
Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be>

Add SDHI[0-3] pinmux support to r8a7795 SoC.
Signed-off-by: NTakeshi Kihara <takeshi.kihara.df@renesas.com>
Signed-off-by: NDirk Behme <dirk.behme@gmail.com>
Reviewed-by: NGeert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be>

Add pins, groups, and a function for SCIF_CLK, which is the external
clock source for the Baud Rate Generator for External Clock (BRG) on
(H)SCIF.
Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be>
Acked-by: NLinus Walleij <linus.walleij@linaro.org>

Extracted from a big patch by Takeshi Kihara.
Signed-off-by: NTakeshi Kihara <takeshi.kihara.df@renesas.com>
[geert: Correct MSIOF3 TXD_A/RXD_A pins]
Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be>

Pins that (1) can be configured as either GPIO or a single peripheral
function, and (2) that don't need configuration in an IPSRx register,
should still be listed in the pinmux_data[] array.

Else selecting the peripheral function fails with e.g.:

    sh-pfc e6060000.pfc: cannot locate data/mark enum_id for mark 1281

(mark 1281 is MSIOF0_SCK_MARK).
Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be>

Many SoC needs each PORT_GP_x() macros, but we can share/reuse
same one.
Signed-off-by: NKuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Acked-by: NLaurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be>

Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be>
Acked-by: NLinus Walleij <linus.walleij@linaro.org>

Cfr. Manual Errata for Rev 0.50 of the R-Car Gen3 datasheet.

This has no user-visible impact.
Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be>
Acked-by: NLinus Walleij <linus.walleij@linaro.org>