1. 29 1月, 2009 16 次提交
  2. 18 12月, 2008 1 次提交
    • M
      x86: fix cpu_mask_to_apicid_and to include cpu_online_mask · a775a38b
      Mike Travis 提交于
      Impact: fix potential APIC crash
      
      In determining the destination apicid, there are usually three cpumasks
      that are considered: the incoming cpumask arg, cfg->domain and the
      cpu_online_mask.  Since we are just introducing the cpu_mask_to_apicid_and
      function, make sure it includes the cpu_online_mask in it's evaluation.
      [Added with this patch.]
      
      There are two io_apic.c functions that did not previously use the
      cpu_online_mask:  setup_IO_APIC_irq and msi_compose_msg.  Both of these
      simply used cpu_mask_to_apicid(cfg->domain & TARGET_CPUS), and all but
      one arch (NUMAQ[*]) returns only online cpus in the TARGET_CPUS mask,
      so the behavior is identical for all cases.
      
      [*: NUMAQ bug?]
      
      Note that alloc_cpumask_var is only used for the 32-bit cases where
      it's highly likely that the cpumask set size will be small and therefore
      CPUMASK_OFFSTACK=n.  But if that's not the case, failing the allocate
      will cause the same return value as the default.
      Signed-off-by: NMike Travis <travis@sgi.com>
      Signed-off-by: NIngo Molnar <mingo@elte.hu>
      a775a38b
  3. 17 12月, 2008 4 次提交
  4. 22 10月, 2008 2 次提交
  5. 16 10月, 2008 1 次提交
  6. 22 7月, 2008 1 次提交
    • Y
      x86: add apic probe for genapic 64bit, v2 · 1b9b89e7
      Yinghai Lu 提交于
      introducing an APIC handling probing abstraction:
      
       static struct genapic *apic_probe[] __initdata = {
      	&apic_x2apic_uv_x,
      	&apic_x2apic_phys,
      	&apic_x2apic_cluster,
      	&apic_physflat,
      	NULL,
       };
      
      This way we can remove UV, x2apic specific code from genapic_64.c and
      move them to their specific genapic files.
      
      [ v2: fix compiling when CONFIG_ACPI is not set ]
      Signed-off-by: NYinghai Lu <yhlu.kernel@gmail.com>
      Cc: Jack Steiner <steiner@sgi.com>
      Cc: Suresh Siddha <suresh.b.siddha@intel.com>
      Signed-off-by: NIngo Molnar <mingo@elte.hu>
      1b9b89e7
  7. 20 7月, 2008 1 次提交
  8. 13 7月, 2008 1 次提交
    • Y
      x86: make 64bit have get_apic_id · f910a9dc
      Yinghai Lu 提交于
      generalize the x2apic code some more.
      
      let read_apic_id become a macro (later on a function/inline)
      GET_APIC_ID(apic_read(APIC_ID))
      
        +#define read_apic_id()  (GET_APIC_ID(apic_read(APIC_ID)))
      
      instead of this weird construct:
      
        -#define read_apic_id  (genapic->read_apic_id)
      Signed-off-by: NYinghai Lu <yhlu.kernel@gmail.com>
      Cc: Suresh Siddha <suresh.b.siddha@intel.com>
      Signed-off-by: NIngo Molnar <mingo@elte.hu>
      f910a9dc
  9. 12 7月, 2008 3 次提交
  10. 17 4月, 2008 2 次提交
  11. 20 10月, 2007 1 次提交
    • M
      x86: convert cpu_to_apicid to be a per cpu variable · 71fff5e6
      Mike Travis 提交于
      This patch converts the x86_cpu_to_apicid array to be a per cpu
      variable. This saves sizeof(apicid) * NR unused cpus.  Access is mostly
      from startup and CPU HOTPLUG functions.
      
      MP_processor_info() is one of the functions that require access to the
      x86_cpu_to_apicid array before the per_cpu data area is setup.  For this
      case, a pointer to the __initdata array is initialized in setup_arch()
      and removed in smp_prepare_cpus() after the per_cpu data area is
      initialized.
      
      A second change is included to change the initial array value of ARCH
      i386 from 0xff to BAD_APICID to be consistent with ARCH x86_64.
      Signed-off-by: NMike Travis <travis@sgi.com>
      Cc: Andi Kleen <ak@suse.de>
      Cc: Christoph Lameter <clameter@sgi.com>
      Cc: "Siddha, Suresh B" <suresh.b.siddha@intel.com>
      Signed-off-by: NAndrew Morton <akpm@linux-foundation.org>
      Signed-off-by: NIngo Molnar <mingo@elte.hu>
      Signed-off-by: NThomas Gleixner <tglx@linutronix.de>
      71fff5e6
  12. 18 10月, 2007 1 次提交
  13. 11 10月, 2007 2 次提交
  14. 03 5月, 2007 3 次提交
  15. 22 10月, 2006 1 次提交
    • E
      [PATCH] x86-64: Put more than one cpu in TARGET_CPUS · 84f404f6
      Eric W. Biederman 提交于
      TARGET_CPUS is the default irq routing poicy.  It specifies which cpus the
      kernel should aim an irq at.  In physflat delivery mode we can route an irq to
      a single cpu.  But that doesn't mean our default policy should only be a
      single cpu is allowed.
      
      By allowing the irq routing code to select from multiple cpus this enables
      systems with more irqs then we can service on a single processor to actually
      work.
      
      I just audited and tested the code and irqbalance doesn't care, and the
      io_apic.c doesn't care if we have extra cpus in the mask.  Everything will use
      or assume we are using the lowest numbered cpu in the mask if we can't use
      them all.
      
      So this should result in no behavior changes except on systems that need it.
      
      Thanks for YH Lu for spotting this problem in his testing.
      
      Cc: Yinghai Lu <yinghai.lu@amd.com>
      Signed-off-by: NEric W. Biederman <ebiederm@xmission.com>
      Signed-off-by: NAndrew Morton <akpm@osdl.org>
      Signed-off-by: NAndi Kleen <ak@suse.de>
      84f404f6