The DISPC's scaling code seems to presume that decimation always
succeeds, and so we always do find a suitable downscaling setup.
However, this is not the case, and the algorithm can fail.

When that happens, the code just proceeds with wrong results, causing
issues later.

Add the necessary checks to bail out if the scaling algorithm failed.
Signed-off-by: NTomi Valkeinen <tomi.valkeinen@ti.com>

The DISPC driver uses 64 bit arithmetic to calculate the required clock
rate for scaling. The code does not seem to work correctly, and instead
calculates with 32 bit numbers, giving wrong result.

Fix the code by typecasting values to u64 first, so that the
calculations do happen in 64 bits.
Signed-off-by: NTomi Valkeinen <tomi.valkeinen@ti.com>

pixel_inc and row_inc work differently on OMAP2/3 and OMAP4+ DSS. On
OMAP2/3 DSS, the pixel_inc is _not_ added by the HW at the end of the
line, after the last pixel, whereas on OMAP4+ it is.

The driver currently works for OMAP4+, but does not handle OMAP2/3
correctly, which leads to tilted image when row_inc is used.

This patch adds a flag to DISPC driver so that the pixel_inc is added
when required.
Signed-off-by: NTomi Valkeinen <tomi.valkeinen@ti.com>

On OMAP3/AM43xx some scaling factors cause underflows/synclosts. After
studying this, I found that sometimes the driver uses three-tap scaling
with downscaling factor smaller than x0.5. This causes issues, as x0.5
is the limit for three-tap scaling.

The driver has FEAT_PARAM_DOWNSCALE parameter, but that seems to be for
five-tap scaling, which allows scaling down to x0.25.

This patch adds checks for both horizontal and vertical scaling. For
horizontal the HW always uses 5 taps, so the limit is x0.25.
Signed-off-by: NTomi Valkeinen <tomi.valkeinen@ti.com>

After calculating the required decimation for scaling, the dispc driver
checks once more if the resulting configuration is valid by calling
check_horiz_timing_omap3().

Earlier calls to this function have correctly used in_width and
in_height as parameters, but the last call uses width and height. This
causes the driver to possibly reject scaling that would work.

This patch fixes the parameters.
Signed-off-by: NTomi Valkeinen <tomi.valkeinen@ti.com>

DISPC needs even input buffer width for YUV modes. The DISPC driver
doesn't check this at the moment (although omapdrm does), but worse,
when DISPC driver does x predecimation the result may be uneven. This
causes sometimes sync losts, underflows, or just visual errors.

This patch makes DISPC driver return an error if the user gives uneven
input width for a YUV buffer. It also makes the input width even in case
of predecimation.
Signed-off-by: NTomi Valkeinen <tomi.valkeinen@ti.com>

Errata i631 description:

"When in YUV4:2:0 format in 1D burst, the DISPC DMA skips lines when
fetching Chroma sampling."

Workaround:

"If YUV4:2:0-1D burst is required: Set
DISPC_VIDp_ATTRIBUTES[22]DOUBLESTRIDE to 0x0 and
DISPC_VIDp_ATTRIBUTES[13:12]ROTATION to 0x1 or 0x3"

The description is somewhat confusing, but testing has shown that DSS
fetches extra rows from memory when using NV12 format in 1D mode. If the
memory after the framebuffer is inaccessible, this leads to OCP errors.

The driver always uses DOUBLESTRIDE=0 when using 1D mode, so we only
need to handle the ROTATION part.

The issue exist on all OMAP4 and OMAP5 based DSS IPs.
Signed-off-by: NTomi Valkeinen <tomi.valkeinen@ti.com>

Add handling of missed events in omap_dss_pm_notif which are
needed to support hibernation (suspend to disk).
Signed-off-by: NGrygorii Strashko <Grygorii.Strashko@linaro.org>
Signed-off-by: NTomi Valkeinen <tomi.valkeinen@ti.com>

We don't need VT switch when suspending/resuming, so disable it. This
speeds up suspend/resume.
Signed-off-by: NTomi Valkeinen <tomi.valkeinen@ti.com>
Cc: NeilBrown <neil@brown.name>

It was found that having two displays enabled and having an NV12 overlay
on one of the displays will cause underflows/synclosts. Debugging this
pointed to some issue with MFLAG.

It is unclear why this issue is happening, but it looks like there is a
HW bug related to MFLAG and FIFO management. Disabling MFLAG makes this
issue go away, but then we lose the benefit of MFLAG. Also forcing MFLAG
always on makes the issue go away.

Also, using certain values for MFLAG_START, MFLAG thresholds and PRELOAD
makes the issue go away, but there was no obvious logic to which values
work and which don't.

As a workaround until more information about this is found, force MFLAG
always on to make NV12 usable.
Signed-off-by: NTomi Valkeinen <tomi.valkeinen@ti.com>

OMAP5 has support for MFLAG feature, which allows DSS to dynamically
increase the priority of DISPC's DMA traffic. At the moment we don't
have support for it.

It was noticed that on DRA7 with high bandwidth use cases we see FIFO
underflows. Implementing MFLAG support removed those underflows.
Interestingly, on OMAP5 uEVM no such overflows were seen.

This patch adds a simple MFLAG implementation, where we use a fixed
MFLAG threshold value based on the FIFO size. The thresholds are set to
4/8 of fifo size for low threshold, and 5/8 of fifo size for high
threshold.
Signed-off-by: NTomi Valkeinen <tomi.valkeinen@ti.com>

At the moment we don't setup FIFO thresholds by default in omapdss. It's
supposed to be done by the user of omapdss. And that is missing from
omapdrm, causing unoptimal thresholds to be used when using omapdrm.

While I believe it's in theory better to allow the user of omapdss to
setup the fifo thresholds, in practice we always use the same values,
and we could as well setup the thresholds in omapdss.

Furthermore, in omapdss init we always swap the FIFO used for GFX and WB
overlays, but we don't swap the FIFO thresholds for those overlays
(which is the reason for omapdrm using unoptimal HW reset values). So
it would make sense to setup the thresholds to account for the swapping
of the FIFOs.

So, this patch adds code to setup default FIFO tresholds at omapdss
init.
Signed-off-by: NTomi Valkeinen <tomi.valkeinen@ti.com>

Dispc driver presumes that the callers handle locking for all normal
functions. However, omapdrm doesn't handle this, and presumes that all
overlay manager registers are private to that overlay manager, and thus
presumes that configurations for overlay managers can be written via
different threads freely.

For many registers the above is true. The exceptions are DISPC_CONTROL
and DISPC_CONFIG registers, which contain bits for both LCD and TV
overlay managers.

Fixing this properly in omapdrm means a big omapdrm rewrite. So, for
now, add locking to dispc for the problematic registers.
Signed-off-by: NTomi Valkeinen <tomi.valkeinen@ti.com>
Reported-by: NSomnath Mukherjee <somnath@ti.com>

omapdrm doesn't always configure the overlays correctly, causing the
overlay setup functions to be called with zero timings. This leads to
division by zero error.

This happens, for example, when a HDMI cable is not connected, but a
user tries to setup a plane with scaling.

Fixing omapdrm is a big job, so for now let's check for the bad timings
in DISPC and return an error.
Signed-off-by: NTomi Valkeinen <tomi.valkeinen@ti.com>

The common 'struct videomode' does not have a flag to select when the
sync signals should be driven.

The default behavior of DISPC HW is to drive the sync signal on the
opposite pixel clock edge from data signal, which is also what the
videomode_to_omap_video_timings() uses.

However, it looks like what panels usually expect is that the data and
sync signals are driven on the same edge, so let's change
videomode_to_omap_video_timings() to set the sync_pclk_edge accordingly.

Note that this only affect panels drivers that use
videomode_to_omap_video_timings(), probably when getting the video
timings directly from DT data. The drivers can still configure the
sync_pclk_edge independently if they so wish.
Signed-off-by: NTomi Valkeinen <tomi.valkeinen@ti.com>

When configuring the lcd timings, instead of writing enum values
directly to the HW, use switch-case to get the value to be programmed.

This is safer and also allows us to change the enum values.
Signed-off-by: NTomi Valkeinen <tomi.valkeinen@ti.com>

DISPC can drive data lines either on rising or falling pixel clock edge,
which can be configured by the user.

Sync lines can also be driven on rising or falling pixel clock edge, but
additionally the HW can be configured to drive the sync lines on
opposite clock edge from the data lines.

This opposite edge setting does not make any sense, as the same effect
can be achieved by just setting the sync lines to be driven on the other
edge compared to the data lines. It feels like some kind of backward
compatibility option, even if all DSS versions seem to have the same
implementation.

To simplify the code and configuration of the signals, and to make the
dispc timings more compatible with what is used on other platforms,
let's just remove the whole opposite-edge support.

The drivers that used OMAPDSS_DRIVE_SIG_OPPOSITE_EDGES setting are
changed so that they use the opposite setting from the data edge.
Signed-off-by: NTomi Valkeinen <tomi.valkeinen@ti.com>

The DISPC driver checks that the buffer address is not 0. However, when
using TILER, the address space is TILER specific and 0 is a valid
address.

Fix the check to allow address of 0 for TILER.
Signed-off-by: NTomi Valkeinen <tomi.valkeinen@ti.com>
Reported-by: Nsrinivas pulukuru <srinivas.pulukuru@ti.com>

omapdss's sysfs directories for displays used to have 'name' file,
giving the name for the display. This file was later renamed to
'display_name' to avoid conflicts with i2c sysfs 'name' file. Looks like
at least xserver-xorg-video-omap3 requires the 'name' file to be
present.

To fix the regression, this patch creates new kobjects for each display,
allowing us to create sysfs directories for the displays. This way we
have the whole directory for omapdss, and there will be no sysfs file
clashes with the underlying display device's sysfs files.

We can thus add the 'name' sysfs file back.
Signed-off-by: NTomi Valkeinen <tomi.valkeinen@ti.com>
Tested-by: NNeilBrown <neilb@suse.de>

It has been observed that the current SDA-HOLD time is too short for
some board/cable/monitor combinations. Increase the SDA-HOLD time to
1000ns.
Signed-off-by: NTomi Valkeinen <tomi.valkeinen@ti.com>

AM43xx supports pixel clock divider of 1, just like all OMAP3+ SoCs. Fix
the minimum divider value.
Signed-off-by: NTomi Valkeinen <tomi.valkeinen@ti.com>

Decrementing the reference count of the previous endpoint node allows to
use the of_graph_get_next_endpoint function in a for_each_... style macro.
All current users of this function that pass a non-NULL prev parameter
(that is, soc_camera and imx-drm) are changed to not decrement the passed
prev argument's refcount themselves.
Signed-off-by: NPhilipp Zabel <p.zabel@pengutronix.de>
Acked-by: NMauro Carvalho Chehab <mchehab@osg.samsung.com>
Acked-by: NMathieu Poirier <mathieu.poirier@linaro.org>
Acked-by: NLaurent Pinchart <laurent.pinchart@ideasonboard.com>
Acked-by: NTomi Valkeinen <tomi.valkeinen@ti.com>

Add support for DRA7xx DPI output.

DRA7xx has three DPI outputs, each of which gets its input from a DISPC
channel. However, DRA72x has only one video PLL, and DRA74x has two
video PLLs. In both cases the video PLLs need to be shared between
multiple outputs. The driver doesn't handle this at the moment.

Also, DRA7xx requires configuring CONTROL module bits to route the clock
from the PLL to the used DISPC channel.
Signed-off-by: NTomi Valkeinen <tomi.valkeinen@ti.com>

Add support for DRA7xx to the HDMI driver.

The HDMI block on DRA7xx is the same as on OMAP5, except we need to
enable and disable the HDMI PLL via the CONTROL module.
Signed-off-by: NTomi Valkeinen <tomi.valkeinen@ti.com>

On DRA7xx, DISPC needs to write output signal polarities not only to a
DISPC register, like for all earlier DSS versions, but to control
module's CTRL_CORE_SMA_SW_1 register.

This patch adds support to write the polarities to control module.
Signed-off-by: NTomi Valkeinen <tomi.valkeinen@ti.com>

Add DRA7xx support to DISPC driver. The DISPC block is the same as on
OMAP5, except the PLL's used for clocking are "videoX", not "dsiX".
Signed-off-by: NTomi Valkeinen <tomi.valkeinen@ti.com>

DRA7xx SoCs have one (DRA72x) or two (DRA74x) video PLLs. They are
basically the same as DSI PLLs on OMAPs, but without the rest of the DSI
hardware. The video PLLs also require some configuration via the CONTROL
module.
Signed-off-by: NTomi Valkeinen <tomi.valkeinen@ti.com>

Add functions which configure the control module register
CTRL_CORE_DSS_PLL_CONTROL found in DRA7xx SoCs. This register configures
whether the PLL registers are accessed internally by DSS, or externally
using OCP2SCP interface. They also configure muxes which route the PLL
output to a particular LCD overlay manager within DSS.
Signed-off-by: NTomi Valkeinen <tomi.valkeinen@ti.com>

Add base support for DRA7xx to DSS core.
Signed-off-by: NTomi Valkeinen <tomi.valkeinen@ti.com>

The OMAP5 HW supports directing DIGIT channel to DPI output, but the
driver doesn't support that. However, we have marked that configuration
as possible in the dss features, so in certain cases the driver tries to
use that configuration, leading to broken display.

Fix the problem by allowing DIGIT channel to go only to HDMI output.
Signed-off-by: NTomi Valkeinen <tomi.valkeinen@ti.com>

The port arrays are constant data, so set them as 'const'.
Signed-off-by: NTomi Valkeinen <tomi.valkeinen@ti.com>

Add a helper function to wait until the PLL's reset is done.
Signed-off-by: NTomi Valkeinen <tomi.valkeinen@ti.com>

In some cases we need global identifiers for the DSS PLLs, for example
when configuring clock muxing on DRA7. For this purpose let's add a
'enum dss_pll_id'.
Signed-off-by: NTomi Valkeinen <tomi.valkeinen@ti.com>

After the commit ef691ff4 (OMAPDSS: DT: Get source endpoint by
matching reg-id) we look for the SDI output using the port number.
However, the SDI driver doesn't set the port number, which causes the
SDI display to not initialize.

Fix this by setting the SDI port number to 1. We use a hardcoded value,
as SDI was used only on OMAP3 and it's always port number 1 there.
Reported-by: NAaro Koskinen <aaro.koskinen@iki.fi>
Reported-by: NPavel Machek <pavel@ucw.cz>
Signed-off-by: NTomi Valkeinen <tomi.valkeinen@ti.com>

The regulator_disable() doesn't accept NULL pointers.
Signed-off-by: NDan Carpenter <dan.carpenter@oracle.com>
Signed-off-by: NTomi Valkeinen <tomi.valkeinen@ti.com>

HDMI hardware parameters structs for OMAP4 and OMAP5 contained two
initializers for 'clkdco_max'. The first one was a remnant with wrong
value.

Remove the extra initializer entries.
Signed-off-by: NTomi Valkeinen <tomi.valkeinen@ti.com>

The bit field for IEC958_AES2_CON_SOURCE is bits 3-0 in
HDMI_CORE_FC_AUDSCHNLS2, not imaginary bits 3-4 (reverse order).
Signed-off-by: NJyri Sarha <jsarha@ti.com>
Signed-off-by: NTomi Valkeinen <tomi.valkeinen@ti.com>

Remove __exit qualifier from hdmi_uninit_output() because it is used
also in omapdss_hdmihw_probe().
Signed-off-by: NJyri Sarha <jsarha@ti.com>
Signed-off-by: NTomi Valkeinen <tomi.valkeinen@ti.com>

Enabling idle mode during audio playback causes the glitches on OMAP5
HDMI. The TRM also suggests to use no-idle for HDMI audio playback.

This patch sets HDMI idle mode to no-idle for the duration of the
playback, and restores it back to original value afterwards.
Signed-off-by: NJyri Sarha <jsarha@ti.com>
Reviewed-by: NMark Brown <broonie@kernel.org>
Signed-off-by: NTomi Valkeinen <tomi.valkeinen@ti.com>

Implements callbacks for OMAP HDMI audio platform driver and registers
it in probe function. Unregistering is done in remove function.
Signed-off-by: NJyri Sarha <jsarha@ti.com>
Reviewed-by: NMark Brown <broonie@kernel.org>
Signed-off-by: NTomi Valkeinen <tomi.valkeinen@ti.com>