1. 11 6月, 2014 2 次提交
  2. 31 5月, 2014 6 次提交
  3. 30 5月, 2014 3 次提交
  4. 29 5月, 2014 7 次提交
  5. 28 5月, 2014 16 次提交
  6. 24 5月, 2014 6 次提交
    • B
      PCI: Add resource allocation comments · 67d29b5c
      Bjorn Helgaas 提交于
      Add comments in the code to match the allocation strategy of 7c671426dfc3
      ("PCI: Restrict 64-bit prefetchable bridge windows to 64-bit resources").
      
      No functional change.
      Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>
      67d29b5c
    • B
      PCI: Simplify __pci_assign_resource() coding style · d3689df0
      Bjorn Helgaas 提交于
      If an allocation succeeds, we can return success immediately.  Then we
      don't have to test for success in the subsequent code.
      
      No functional change.
      Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>
      d3689df0
    • B
      PCI: Change pbus_size_mem() return values to be more conventional · 30afe8d0
      Bjorn Helgaas 提交于
      pbus_size_mem() previously returned 0 for failure and 1 for success.
      Change it to return -ENOSPC for failure and 0 for success.
      
      No functional change.
      Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>
      30afe8d0
    • Y
      PCI: Restrict 64-bit prefetchable bridge windows to 64-bit resources · 5b285415
      Yinghai Lu 提交于
      This patch changes the way we handle 64-bit prefetchable bridge windows to
      make it more likely that we can assign space to all devices.
      
      Previously we put all prefetchable resources in the prefetchable bridge
      window.  If any of those resources was 32-bit only, we restricted the
      window to be below 4GB.
      
      After this patch, we only put 64-bit prefetchable resources in a 64-bit
      prefetchable window.  We put all 32-bit prefetchable resources in the
      non-prefetchable window, even if there are no 64-bit prefetchable
      resources.
      
      With the previous approach, if there was a 32-bit prefetchable resource
      behind a bridge, we forced the bridge's prefetchable window below 4GB,
      which meant that even if there was plenty of space above 4GB available, we
      couldn't use it, and assignment of large 64-bit resources could fail, as
      in the bugzilla below.
      
      The new strategy is:
      
        1) If the prefetchable window is 64 bits wide, we put only 64-bit
           prefetchable resources in it.  Any 32-bit prefetchable resources go in
           the non-prefetchable window.
      
        2) If the prefetchable window is 32 bits wide, we put both 32- and 64-bit
           prefetchable resources in it.
      
        3) If there is no prefetchable window, all MMIO resources go in the
           non-prefetchable window.
      
      This reduces performance for 32-bit prefetchable resources below a bridge
      with a 64-bit prefetchable window.  We previously assigned prefetchable
      space, but now we'll assign non-prefetchable space.  This is the case even
      if there are no 64-bit prefetchable resources, or if they would all fit
      below 4GB.  In those cases, the old strategy would work and would have
      better performance.
      
      [bhelgaas: write changelog, add bugzilla link, fold in mem64_mask removal]
      Link: https://bugzilla.kernel.org/show_bug.cgi?id=74151Tested-by: NGuo Chao <yan@linux.vnet.ibm.com>
      Tested-by: NWei Yang <weiyang@linux.vnet.ibm.com>
      Signed-off-by: NYinghai Lu <yinghai@kernel.org>
      Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>
      5b285415
    • A
      PCI: Support BAR sizes up to 8GB · 14c8530d
      Alan 提交于
      This is needed for some of the Xeon Phi type systems.
      
      [bhelgaas: added Nikhil, use ARRAY_SIZE() to connect with decl, folded in
      Kevin's "order < 0" fix to ARRAY_SIZE() usage]
      Signed-off-by: NNikhil P Rao <nikhil.rao@intel.com>
      Signed-off-by: NAlan Cox <alan@linux.intel.com>
      Signed-off-by: NKevin Hilman <khilman@linaro.org>
      Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>
      14c8530d
    • B
      PCI: Don't add disabled subtractive decode bus resources · d739a099
      Bjorn Helgaas 提交于
      For a subtractive decode bridge, we previously added and printed all
      resources of the primary bus, even if they were not valid.  In the example
      below, the bridge 00:1c.3 has no windows enabled, so there are no valid
      resources on bus 02.  But since 02:00.0 is subtractive decode bridge, we
      add and print all those invalid resources, which don't really make sense:
      
        pci 0000:00:1c.3: PCI bridge to [bus 02-03]
        pci 0000:02:00.0: PCI bridge to [bus 03] (subtractive decode)
        pci 0000:02:00.0:   bridge window [??? 0x00000000 flags 0x0] (subtractive decode)
      
      Add and print the subtractively-decoded resources only if they are valid.
      
      There's an example in the dmesg log attached to the bugzilla below (but
      this patch doesn't fix the bug reported there).
      
      Link: https://bugzilla.kernel.org/show_bug.cgi?id=73141Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>
      d739a099