1. 25 8月, 2015 23 次提交
  2. 22 8月, 2015 2 次提交
    • A
      drm/amdgpu: Don't link train DisplayPort on HPD until we get the dpcd · a887adad
      Alex Deucher 提交于
      This is a port of:
      DRM - radeon: Don't link train DisplayPort on HPD until we get the dpcd
      to amdgpu.
      Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
      Cc: stable@vger.kernel.org
      a887adad
    • S
      DRM - radeon: Don't link train DisplayPort on HPD until we get the dpcd · 924f92bf
      Stephen Chandler Paul 提交于
      Most of the time this isn't an issue since hotplugging an adaptor will
      trigger a crtc mode change which in turn, causes the driver to probe
      every DisplayPort for a dpcd. However, in cases where hotplugging
      doesn't cause a mode change (specifically when one unplugs a monitor
      from a DisplayPort connector, then plugs that same monitor back in
      seconds later on the same port without any other monitors connected), we
      never probe for the dpcd before starting the initial link training. What
      happens from there looks like this:
      
      	- GPU has only one monitor connected. It's connected via
      	  DisplayPort, and does not go through an adaptor of any sort.
      
      	- User unplugs DisplayPort connector from GPU.
      
      	- Change in HPD is detected by the driver, we probe every
      	  DisplayPort for a possible connection.
      
      	- Probe the port the user originally had the monitor connected
      	  on for it's dpcd. This fails, and we clear the first (and only
      	  the first) byte of the dpcd to indicate we no longer have a
      	  dpcd for this port.
      
      	- User plugs the previously disconnected monitor back into the
      	  same DisplayPort.
      
      	- radeon_connector_hotplug() is called before everyone else,
      	  and tries to handle the link training. Since only the first
      	  byte of the dpcd is zeroed, the driver is able to complete
      	  link training but does so against the wrong dpcd, causing it
      	  to initialize the link with the wrong settings.
      
      	- Display stays blank (usually), dpcd is probed after the
      	  initial link training, and the driver prints no obvious
      	  messages to the log.
      
      In theory, since only one byte of the dpcd is chopped off (specifically,
      the byte that contains the revision information for DisplayPort), it's
      not entirely impossible that this bug may not show on certain monitors.
      For instance, the only reason this bug was visible on my ASUS PB238
      monitor was due to the fact that this monitor using the enhanced framing
      symbol sequence, the flag for which is ignored if the radeon driver
      thinks that the DisplayPort version is below 1.1.
      Signed-off-by: NStephen Chandler Paul <cpaul@redhat.com>
      Reviewed-by: NJerome Glisse <jglisse@redhat.com>
      Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
      Cc: stable@vger.kernel.org
      924f92bf
  3. 21 8月, 2015 9 次提交
  4. 20 8月, 2015 1 次提交
    • J
      drm/layerscape: Add Freescale DCU DRM driver · 109eee2f
      Jianwei Wang 提交于
      This patch add support for Two Dimensional Animation and Compositing
      Engine (2D-ACE) on the Freescale SoCs.
      
      2D-ACE is a Freescale display controller. 2D-ACE describes
      the functionality of the module extremely well its name is a value
      that cannot be used as a token in programming languages.
      Instead the valid token "DCU" is used to tag the register names and
      function names.
      
      The Display Controller Unit (DCU) module is a system master that
      fetches graphics stored in internal or external memory and displays
      them on a TFT LCD panel. A wide range of panel sizes is supported
      and the timing of the interface signals is highly configurable.
      Graphics are read directly from memory and then blended in real-time,
      which allows for dynamic content creation with minimal CPU
      intervention.
      
      The features:
      (1) Full RGB888 output to TFT LCD panel.
      (2) Blending of each pixel using up to 4 source layers
      dependent
      on size of panel.
      (3) Each graphic layer can be placed with one pixel resolution
      in either axis.
      (4) Each graphic layer support RGB565 and RGB888 direct colors
      without alpha channel and BGRA8888 BGRA4444 ARGB1555 direct
      colors
      with an alpha channel and YUV422 format.
      (5) Each graphic layer support alpha blending with 8-bit
      resolution.
      This is a simplified version, only one primary plane, one
      framebuffer, one crtc, one connector and one encoder for TFT
      LCD panel.
      Signed-off-by: NAlison Wang <b18965@freescale.com>
      Signed-off-by: NXiubo Li <lixiubo@cmss.chinamobile.com>
      Signed-off-by: NJianwei Wang <jianwei.wang.chn@gmail.com>
      Acked-by: NDaniel Vetter <daniel.vetter@ffwll.ch>
      109eee2f
  5. 18 8月, 2015 5 次提交