sdma_request_channel sets the default priority. sdma_alloc_chan_resources
should call sdma_set_channel_priority thereafter to over write it.
Signed-off-by: NRichard Zhao <richard.zhao@linaro.org>
Acked-by: NShawn Guo <shawn.guo@linaro.org>
Signed-off-by: NVinod Koul <vinod.koul@linux.intel.com>

use readl_relaxed/writel_relaxed in most places, and use writel when
enable channel, because it needs memory barrier.
Signed-off-by: NRichard Zhao <richard.zhao@linaro.org>
Signed-off-by: NVinod Koul <vinod.koul@linux.intel.com>

Let all enable channel code call sdma_enable_channel.
Signed-off-by: NRichard Zhao <richard.zhao@linaro.org>
Acked-by: NShawn Guo <shawn.guo@linaro.org>
Acked-by: NSascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: NVinod Koul <vinod.koul@linux.intel.com>

The DMA engine API requires that transfers are started in issue_pending
instead of tx_submit. Fix this.
Signed-off-by: NSascha Hauer <s.hauer@pengutronix.de>
[corrected change log to DMA engine API insteadof DMA API]
Signed-off-by: NVinod Koul <vinod.koul@linux.intel.com>

mx53_loco: fix deadlock report from sdma_tx_submit() during boot

BugLink: http://bugs.launchpad.net/bugs/878701

Adjust to use spin_lock_irqsave()/spin_unlock_irqresotre(), so to
make it safe when called from interrupt context.
Signed-off-by: NHaitao Zhang <haitao.zhang@linaro.org>
Signed-off-by: NEric Miao <eric.miao@linaro.org>
Signed-off-by: NRichard Zhao <richard.zhao@linaro.org>
Acked-by: NSascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: NVinod Koul <vinod.koul@linux.intel.com>

When we use the SDMA in the UART driver(such as imx6q), we will
meet one situation:
  Assume we set 64 bytes for the RX DMA buffer.
  The RX DMA buffer has received some data, but not full.
  An Aging DMA request will be received by the SDMA controller if we enable the
  IDDMAEN(UCR4[6]) in this case.

So the UART driver needs to know the count of the real received bytes,
and push them to upper layer.

Add two new fields to sdmac, and update the `residue` in sdma_tx_status().
Signed-off-by: NHuang Shijie <b32955@freescale.com>
Signed-off-by: NVinod Koul <vinod.koul@linux.intel.com>

Set the right DMA direction in the sdma_control(), else
we will get the wrong log when enable the DYNAMIC_DEBUG.
Signed-off-by: NHuang Shijie <b32955@freescale.com>
Signed-off-by: NVinod Koul <vinod.koul@linux.intel.com>

Fix files that were implicitly using module.h but not
calling it out for inclusion directly.  We'll break those
once we remove the implicit presence otherwise

[With input from Uwe Kleine-König <u.kleine-koenig@pengutronix.de>]
Signed-off-by: NPaul Gortmaker <paul.gortmaker@windriver.com>

fixup usage of dma direction by introducing dma_transfer_direction,
this patch moves dma/drivers/* to use new enum

Cc: Jassi Brar <jaswinder.singh@linaro.org>
Cc: Russell King <rmk+kernel@arm.linux.org.uk>
Cc: Viresh Kumar <viresh.kumar@st.com>
Cc: Linus Walleij <linus.walleij@linaro.org>
Cc: Nicolas Ferre <nicolas.ferre@atmel.com>
Cc: Mika Westerberg <mika.westerberg@iki.fi>
Cc: H Hartley Sweeten <hartleys@visionengravers.com>
Cc: Li Yang <leoli@freescale.com>
Cc: Zhang Wei <zw@zh-kernel.org>
Cc: Sascha Hauer <s.hauer@pengutronix.de>
Cc: Guennadi Liakhovetski <g.liakhovetski@gmx.de>
Cc: Shawn Guo <shawn.guo@freescale.com>
Cc: Yong Wang <yong.y.wang@intel.com>
Cc: Tomoya MORINAGA <tomoya-linux@dsn.lapis-semi.com>
Cc: Boojin Kim <boojin.kim@samsung.com>
Cc: Barry Song <Baohua.Song@csr.com>
Acked-by: NMika Westerberg <mika.westerberg@iki.fi>
Acked-by: NLinus Walleij <linus.walleij@linaro.org>
Acked-by: NViresh Kumar <viresh.kumar@st.com>
Acked-by: NNicolas Ferre <nicolas.ferre@atmel.com>
Signed-off-by: NVinod Koul <vinod.koul@linux.intel.com>

Add missing include of linux/module.h to fix build error.
Signed-off-by: NAxel Lin <axel.lin@gmail.com>
Acked-by: NWolfram Sang <w.sang@pengutronix.de>
Signed-off-by: NVinod Koul <vinod.koul@intel.com>

The firmware blob may not be available when the driver
probes. Instead of blocking the whole kernel use
request_firmware_nowait() and continue without firmware.
The ROM scripts can already be used then if available.
For the devicetree case the ROM scripts are not available,
still the probe function should not block. The driver
will be unusable in this case, but we have no way of
detecting this properly. The configuration of the dma
channels will fail, so nothing bad should happen.
Signed-off-by: NSascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: NVinod Koul <vinod.koul@intel.com>

If we do not have a firmare script for a given transfer,
the setup of this channel must fail. For this the script
addresses have to be < 0 initially, not 0.
Signed-off-by: NSascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: NVinod Koul <vinod.koul@intel.com>

channel0 of the sdma engine is the configuration channel. It
is a shared resource and thus must be protected by a mutex.
Signed-off-by: NSascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: NVinod Koul <vinod.koul@intel.com>

It adds device tree probe support for imx-sdma driver.
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>
Cc: Grant Likely <grant.likely@secretlab.ca>
Cc: Vinod Koul <vinod.koul@intel.com>
Cc: Sascha Hauer <s.hauer@pengutronix.de>
Acked-by: NVinod Koul <vinod.koul@intel.com>

It does not need to allocate space and copy fw_name in function
sdma_get_firmware().
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>
Cc: Vinod Koul <vinod.koul@intel.com>
Cc: Sascha Hauer <s.hauer@pengutronix.de>
Acked-by: NVinod Koul <vinod.koul@intel.com>

It might be not good to use software defined version to identify sdma
device type, when hardware does not define such version.  Instead,
soc name is stable enough to define the device type.

The patch uses platform_device_id rather than version number passed
by platform data to identify sdma device type/version.
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>
Cc: Vinod Koul <vinod.koul@intel.com>
Cc: Sascha Hauer <s.hauer@pengutronix.de>
Acked-by: NGrant Likely <grant.likely@secretlab.ca>
Acked-by: NVinod Koul <vinod.koul@intel.com>

Signed-off-by: NAxel Lin <axel.lin@gmail.com>
Acked-by: NSascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: NVinod Koul <vinod.koul@intel.com>

It is not good to have cpu_name and to_version encoded into sdma
firmware name as variables.  For example, there are three TOs of
imx51 soc, the sdma script never changes since TO1, which means
all three TOs of imx51 uses TO1 version of sdma script.  But we
have to prepare three identical firmwares, sdma-imx51-to1.bin
sdma-imx51-to2.bin and sdma-imx51-to3.bin, to have the kernel
capable of running on all three TOs.

The patch removes cpu_name and to_version from sdma platform data,
and instead uses fw_name to pass the firmware name, so that we can
pass the TO version where it's relevant and skip it where only one
firmware exists.
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>
Acked-by: NVinod Koul <vinod.koul@intel.com>
Signed-off-by: NSascha Hauer <s.hauer@pengutronix.de>

As per the reference manual, bit "L" should be set while bit "C"
should be cleared for the last buffer descriptor in the non-cyclic
chain, so that sdma can stop trying to find the next BD and end
the transfer.

In case of sdma_prep_slave_sg(), BD_LAST needs to be set and BD_CONT
be cleared for the last BD.
Signed-off-by: NShawn Guo <shawn.guo@freescale.com>
Signed-off-by: NSascha Hauer <s.hauer@pengutronix.de>

sdma_handle_channel_loop() is the handler of cyclic tx.  One period
success does not really mean the success of the tx.  Instead of
DMA_SUCCESS, DMA_IN_PROGRESS should be the one to tell.
Signed-off-by: NShawn Guo <shawn.guo@freescale.com>
Signed-off-by: NSascha Hauer <s.hauer@pengutronix.de>

The sdmac->status was designed to reflect the status of the tx,
so simply return it in sdma_tx_status().  Then dma client can call
dma_async_is_tx_complete() to know the status of the tx.
Signed-off-by: NShawn Guo <shawn.guo@freescale.com>
Signed-off-by: NSascha Hauer <s.hauer@pengutronix.de>

sdma_prep_dma_cyclic() sets sdmac->status to DMA_ERROR in err_out,
and sdma_prep_slave_sg() needs to do the same.  Otherwise,
sdmac->status stays at DMA_IN_PROGRESS, which will make the function
return immediately next time it gets called.
Signed-off-by: NShawn Guo <shawn.guo@freescale.com>
Signed-off-by: NSascha Hauer <s.hauer@pengutronix.de>

This is a leftover from the time that the driver did not have
sdma_prep_dma_cyclic callback and implemented sound dma as a looped
sg chain.  And it can be removed now.
Signed-off-by: NShawn Guo <shawn.guo@freescale.com>
Signed-off-by: NSascha Hauer <s.hauer@pengutronix.de>

We need channel 0 of the sdma engine for internal purposes. We
accomplished this by calling dma_request_channel() in the probe
function. This does not work when multiple dma engines are
present which is the case when IPU support for i.MX31/35 is
compiled in. So instead of registering channel 0 and reserving
it afterwards simply do not register it in the first place.
With this the dmaengine channel counting does not match sdma
channel counting anymore, so we have to use sdma channel counting
in the driver.
Signed-off-by: NSascha Hauer <s.hauer@pengutronix.de>

The capabilities are device specific fields, not channel specific fields.
Signed-off-by: NSascha Hauer <s.hauer@pengutronix.de>

This is bogus as the dmaengine core will overwrite this field.
Signed-off-by: NSascha Hauer <s.hauer@pengutronix.de>

This patch lets sdma_prep_slave_sg fail if the entries of an
sg list do not start on multiples of the word size or if the
lengths are not multiple of the word size.
Also, catch the previously unhandled DMA_SLAVE_BUSWIDTH_8_BYTES
and DMA_SLAVE_BUSWIDTH_UNDEFINED cases.
Signed-off-by: NSascha Hauer <s.hauer@pengutronix.de>

Signed-off-by: NSascha Hauer <s.hauer@pengutronix.de>

Variable name sdma and sdmac are consistently used as the pointer to
sdma_engine and sdma_channel respectively throughout the file.  The
patch fixes the inconsistency seen in function sdma_assign_cookie().
Signed-off-by: NShawn Guo <shawn.guo@freescale.com>
Signed-off-by: NDan Williams <dan.j.williams@intel.com>

Signed-off-by: NShawn Guo <shawn.guo@freescale.com>
Acked-by: NUwe Kleine-König <u.kleine-koenig@pengutronix.de>
Signed-off-by: NDan Williams <dan.j.williams@intel.com>

When loading the microcode to the SDMA engine we have to use
the ram_code_start_addr found in the firmware image. The copy
in the sdma engine is not initialized correctly. This is broken
since:
5b28aa31 dmaengine i.MX SDMA: Allow to run without firmware
Signed-off-by: NSascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: NDan Williams <dan.j.williams@intel.com>

The firmware framework gets initialized during fs_initcall time, so
we are not allowed to call request_firmware earlier.
Signed-off-by: NSascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: NDan Williams <dan.j.williams@intel.com>

Currently while submitting scatterlists with more than one SG
entry the DMA buffer address from the first SG entry is inserted
into all initialized DMA buffer descriptors. This is due to the
typo in the for_each_sg() loop where the scatterlist pointer is
used for obtaining the DMA buffer address and _not_ the SG list
iterator.

As a result all received data will be written only into the first
DMA buffer while reading. While writing the data from the first
DMA buffer is send to the device multiple times. This caused
the filesystem destruction on the MMC card when using DMA in
mxcmmc driver.
Signed-off-by: NAnatolij Gustschin <agust@denx.de>
Acked-by: NSascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: NDan Williams <dan.j.williams@intel.com>

The SDMA firmware consists of a ROM part and a RAM part.
The ROM part is always present in the SDMA engine and
is sufficient for many cases.
This patch allows to pass in platform data containing
the script addresses in ROM, so loading a firmware is
optional now.
Signed-off-by: NSascha Hauer <s.hauer@pengutronix.de>
Acked-by: NDan Williams <dan.j.williams@intel.com>

This patch adds support for the Freescale i.MX SDMA engine.

The SDMA engine is a scatter/gather DMA engine which is implemented
as a seperate coprocessor. SDMA needs its own firmware which is
requested using the standard request_firmware mechanism. The firmware
has different entry points for each peripheral type, so drivers
have to pass the peripheral type to the DMA engine which in turn
picks the correct firmware entry point from a table contained in
the firmware image itself.
The original Freescale code also supports support for transfering
data to the internal SRAM which needs different entry points to
the firmware. Support for this is currently not implemented. Also,
support for the ASRC (asymmetric sample rate converter) is skipped.

I took a very simple approach to implement dmaengine support. Only
a single descriptor is statically assigned to a each channel. This
means that transfers can't be queued up but only a single transfer
is in progress. This simplifies implementation a lot and is sufficient
for the usual device/memory transfers.
Signed-off-by: NSascha Hauer <s.hauer@pengutronix.de>
Reviewed-by: NLinus Walleij <linus.ml.walleij@gmail.com>
Signed-off-by: NDan Williams <dan.j.williams@intel.com>