1. 22 10月, 2014 1 次提交
    • C
      clk: sunxi: Add support for A80 basic bus clocks · 3b2bd70f
      Chen-Yu Tsai 提交于
      The A80 SoC has 12 PLL clocks, 3 AHB clocks, 2 APB clocks, and a
      new "GT" bus, which I assume is some kind of data bus connecting
      the processor cores, memory and various busses. Also there is a
      bus clock for a ARM CCI400 module.
      
      As far as I can tell, the GT bus and CCI400 bus clock must be
      protected.
      
      This patch adds driver support for peripheral related PLLs and
      bus clocks on the A80. The GT and CCI400 clocks are added as well
      as these 2 along with the PLLs they are clocked from must not be
      disabled.
      Signed-off-by: NChen-Yu Tsai <wens@csie.org>
      Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>
      3b2bd70f
  2. 27 9月, 2014 2 次提交
  3. 07 7月, 2014 1 次提交
  4. 11 6月, 2014 3 次提交
  5. 27 3月, 2013 1 次提交
    • E
      clk: arm: sunxi: Add a new clock driver for sunxi SOCs · e874a669
      Emilio López 提交于
      This commit implements the base CPU clocks for sunxi devices. It has
      been tested using a slightly modified cpufreq driver from the
      linux-sunxi 3.0 tree.
      
      Additionally, document the new bindings introduced by this patch.
      
      Idling:
          / # cat /sys/kernel/debug/clk/clk_summary
             clock                        enable_cnt  prepare_cnt  rate
          ---------------------------------------------------------------------
           osc32k                         0           0            32768
           osc24M_fixed                   0           0            24000000
              osc24M                      0           0            24000000
                 apb1_mux                 0           0            24000000
                    apb1                  0           0            24000000
                 pll1                     0           0            60000000
                    cpu                   0           0            60000000
                       axi                0           0            60000000
                          ahb             0           0            60000000
                             apb0         0           0            30000000
           dummy                          0           0            0
      
      After "yes >/dev/null &":
          / # cat /sys/kernel/debug/clk/clk_summary
             clock                        enable_cnt  prepare_cnt  rate
          ---------------------------------------------------------------------
           osc32k                         0           0            32768
           osc24M_fixed                   0           0            24000000
              osc24M                      0           0            24000000
                 apb1_mux                 0           0            24000000
                    apb1                  0           0            24000000
                 pll1                     0           0            1008000000
                    cpu                   0           0            1008000000
                       axi                0           0            336000000
                          ahb             0           0            168000000
                             apb0         0           0            84000000
           dummy                          0           0            0
      Signed-off-by: NEmilio López <emilio@elopez.com.ar>
      Acked-by: NMaxime Ripard <maxime.ripard@free-electrons.com>
      Signed-off-by: NMike Turquette <mturquette@linaro.org>
      e874a669