Skip to content

cloud-kernel
cloud-kernel

openanolis / cloud-kernel
大约 1 年 前同步成功

通知 153
Star 36
Fork 7
cloud-kernel
cloud-kernel

体验新版 GitCode，发现更多精彩内容 >>

切换分支/标签
  1. 12 6月, 2015 1 次提交
  3. 11 6月, 2015 1 次提交
  5. 10 6月, 2015 1 次提交
  7. 09 6月, 2015 2 次提交
  9. 04 6月, 2015 1 次提交
  11. 31 5月, 2015 1 次提交
  13. 30 5月, 2015 1 次提交
  15. 26 5月, 2015 1 次提交
  17. 23 5月, 2015 1 次提交
  19. 16 5月, 2015 4 次提交
  21. 15 5月, 2015 1 次提交
    • F
      of: mdio: Add a "broken-turn-around" property · ab6016e0
      由 Florian Fainelli 提交于 
      Some Ethernet PHY devices/switches may not properly release the MDIO bus
during turn-around time, and fail to drive it low, which can be seen by
some controllers as a read failure, while the data clocked in is still
correct.

Add a boolean property "broken-turn-around" which is parsed by the
generic MDIO bus probing code and will set the corresponding bit in the
MDIO bus phy_ignore_ta_mask bitmask for MDIO bus drivers to utilize that
information.
Signed-off-by: NFlorian Fainelli <f.fainelli@gmail.com>
Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      ab6016e0
  23. 10 5月, 2015 1 次提交
  25. 09 5月, 2015 1 次提交
  27. 06 5月, 2015 1 次提交
  29. 05 5月, 2015 1 次提交
    • S
      bus: omap_l3_noc: Fix master id address decoding for OMAP5 · e7309c26
      由 Suman Anna 提交于 
      The L3 Error handling on OMAP5 for the most part is very similar
to that of OMAP4, and had leveraged common data structures and
register layout definitions so far. Upon closer inspection, there
are a few minor differences causing an incorrect decoding and
reporting of the master NIU upon an error:

  1. The L3_TARG_STDERRLOG_MSTADDR.STDERRLOG_MSTADDR occupies
     11 bits on OMAP5 as against 8 bits on OMAP4, with the master
     NIU connID encoded in the 6 MSBs of the STDERRLOG_MSTADDR
     field.
  2. The CLK3 FlagMux component has 1 input source on OMAP4 and 3
     input sources on OMAP5. The common DEBUGSS source is at a
     different input on each SoC.

Fix the above issues by using a OMAP5-specific compatible property
and using SoC-specific data where there are differences.
Signed-off-by: NSuman Anna <s-anna@ti.com>
Acked-by: NNishanth Menon <nm@ti.com>
Signed-off-by: NTony Lindgren <tony@atomide.com>
      e7309c26
  31. 27 4月, 2015 1 次提交
  33. 23 4月, 2015 1 次提交
  35. 22 4月, 2015 1 次提交
  37. 20 4月, 2015 2 次提交
  39. 17 4月, 2015 3 次提交
  41. 16 4月, 2015 1 次提交
    • M
      Doc: dt: arch_timer: discourage clock-frequency use · 4155fc07
      由 Mark Rutland 提交于 
      The ARM Generic Timer (AKA the architected timer, arm_arch_timer)
features a CPU register (CNTFRQ) which firmware is intended to
initialize, and non-secure software can read to determine the frequency
of the timer. On CPUs with secure state, this register cannot be written
from non-secure states.

The firmware of early SoCs featuring the timer did not correctly
initialize CNTFRQ correctly on all CPUs, requiring the frequency to be
described in DT as a workaround. This workaround is not complete however
as it is exposed to all software in a privileged non-secure mode
(including guests running under a hypervisor). The firmware and DTs for
recent SoCs have followed the example set by these early SoCs.

This patch updates the arch timer binding documentation to make it
clearer that the use of the clock-frequency property is a poor
work-around. The MMIO generic timer binding is similarly updated, though
this is less of a concern as there is generally no need to expose the
MMIO timers to guest OSs.
Signed-off-by: NMark Rutland <mark.rutland@arm.com>
Acked-by: NCatalin Marinas <catalin.marinas@arm.com>
Acked-by: NMarc Zyngier <marc.zyngier@arm.com>
Acked-by: NOlof Johansson <olof@lixom.net>
Acked-by: NStephen Boyd <sboyd@codeaurora.org>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: Will Deacon <will.deacon@arm.com>
Signed-off-by: NRob Herring <robh@kernel.org>
      4155fc07
  43. 15 4月, 2015 2 次提交
  45. 13 4月, 2015 1 次提交
  47. 11 4月, 2015 4 次提交
  49. 10 4月, 2015 2 次提交
  51. 09 4月, 2015 3 次提交