1. 25 11月, 2014 1 次提交
    • G
      net/smsc911x: Add minimal runtime PM support · 3a611e26
      Geert Uytterhoeven 提交于
      Add minimal runtime PM support (enable on probe, disable on remove), to
      ensure proper operation with a parent device that uses runtime PM.
      
      This is needed on systems where the external bus controller module of
      the SoC is contained in a PM domain and/or has a gateable functional
      clock. In such cases, before accessing any device connected to the
      external bus, the PM domain must be powered up, and/or the functional
      clock must be enabled, which is typically handled through runtime PM by
      the bus controller driver.
      
      An example of this is the kzm9g development board, where an smsc9220
      Ethernet controller is connected to the Bus State Controller (BSC) of a
      Renesas sh73a0 SoC.
      Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be>
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      3a611e26
  2. 14 11月, 2014 3 次提交
    • E
      smsc911x: power-up phydev before doing a software reset. · ccf899a2
      Enric Balletbo i Serra 提交于
      With commit be9dad1f ("net: phy: suspend phydev when going
      to HALTED"), the PHY device will be put in a low-power mode using
      BMCR_PDOWN if the the interface is set down. The smsc911x driver does
      a software_reset opening the device driver (ndo_open). In such case,
      the PHY must be powered-up before access to any register and before
      calling the software_reset function. Otherwise, as the PHY is powered
      down the software reset fails and the interface can not be enabled
      again.
      
      This patch fixes this scenario that is easy to reproduce setting down
      the network interface and setting up again.
      
          $ ifconfig eth0 down
          $ ifconfig eth0 up
          ifconfig: SIOCSIFFLAGS: Input/output error
      Signed-off-by: NEnric Balletbo i Serra <eballetbo@iseebcn.com>
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      ccf899a2
    • A
      net/smsc911x: Fix delays in the PHY enable/disable routines · 6ff53fd3
      Alexander Kochetkov 提交于
      Increased delay in the smsc911x_phy_disable_energy_detect (from 1ms to 2ms).
      Dropped delays in the smsc911x_phy_enable_energy_detect (100ms and 1ms).
      
      The patch affect SMSC LAN generation 4 chips with integrated PHY (LAN9221).
      
      I saw problems with soft reset due to wrong udelay timings.
      After I fixed udelay, I measured the time needed to bring integrated PHY
      from power-down to operational mode (the time beetween clearing EDPWRDOWN
      bit and soft reset complete event). I got 1ms (measured using ktime_get).
      The value is equal to the current value (1ms) used in the
      smsc911x_phy_disable_energy_detect. It is near the upper bound and in order
      to avoid rare soft reset faults it is doubled (2ms).
      
      I don't know official timing for bringing up integrated PHY as specs doesn't
      clarify this (or may be I didn't found).
      
      It looks safe to drop delays before and after setting EDPWRDOWN bit
      (enable PHY power-down mode). I didn't saw any regressions with the patch.
      
      The patch was reviewed by Steve Glendinning and Microchip Team.
      Signed-off-by: NAlexander Kochetkov <al.kochet@gmail.com>
      Acked-by: NSteve Glendinning <steve.glendinning@shawell.net>
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      6ff53fd3
    • A
      net/smsc911x: Fix rare soft reset timeout issue due to PHY power-down mode · 242bcd5b
      Alexander Kochetkov 提交于
      The patch affect SMSC LAN generation 4 chips with integrated PHY (LAN9221).
      
      It is possible that PHY could enter power-down mode (ENERGYON clear),
      between ENERGYON bit check in smsc911x_phy_disable_energy_detect and SRST
      bit set in smsc911x_soft_reset. This could happen, for example, if someone
      disconnect ethernet cable between the checks. The PHY in a power-down mode
      would prevent the MAC portion of chip to be software reseted.
      
      Initially found by code review, confirmed later using test case.
      
      This is low probability issue, and in order to reproduce it you have to
      run the script:
      
      while true; do
      	ifconfig eth0 down
      	ifconfig eth0 up || break
      done
      
      While the script is running you have to plug/unplug ethernet cable many
      times (using gpio controlled ethernet switch, for example) until get:
      
      [ 4516.477783] ADDRCONF(NETDEV_UP): eth0: link is not ready
      [ 4516.512207] smsc911x smsc911x.0: eth0: SMSC911x/921x identified at 0xce006000, IRQ: 336
      [ 4516.524658] ADDRCONF(NETDEV_UP): eth0: link is not ready
      [ 4516.559082] smsc911x smsc911x.0: eth0: SMSC911x/921x identified at 0xce006000, IRQ: 336
      [ 4516.571990] ADDRCONF(NETDEV_UP): eth0: link is not ready
      ifconfig: SIOCSIFFLAGS: Input/output error
      
      The patch was reviewed by Steve Glendinning and Microchip Team.
      Signed-off-by: NAlexander Kochetkov <al.kochet@gmail.com>
      Acked-by: NSteve Glendinning <steve.glendinning@shawell.net>
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      242bcd5b
  3. 04 10月, 2014 1 次提交
  4. 04 6月, 2014 1 次提交
  5. 27 3月, 2014 2 次提交
  6. 25 3月, 2014 1 次提交
  7. 21 3月, 2014 1 次提交
  8. 07 12月, 2013 1 次提交
    • J
      ethernet: Fix FSF address in file headers · 0ab75ae8
      Jeff Kirsher 提交于
      Several files refer to an old address for the Free Software Foundation
      in the file header comment.  Resolve by replacing the address with
      the URL <http://www.gnu.org/licenses/> so that we do not have to keep
      updating the header comments anytime the address changes.
      
      CC: Santosh Raspatur <santosh@chelsio.com>
      CC: Dimitris Michailidis <dm@chelsio.com>
      CC: Michael Chan <mchan@broadcom.com>
      CC: Santiago Leon <santil@linux.vnet.ibm.com>
      CC: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
      CC: Olof Johansson <olof@lixom.net>
      CC: Manish Chopra <manish.chopra@qlogic.com>
      CC: Sony Chacko <sony.chacko@qlogic.com>
      CC: Rajesh Borundia <rajesh.borundia@qlogic.com>
      CC: Nicolas Pitre <nico@fluxnic.net>
      CC: Steve Glendinning <steve.glendinning@shawell.net>
      Signed-off-by: NJeff Kirsher <jeffrey.t.kirsher@intel.com>
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      0ab75ae8
  9. 02 11月, 2013 1 次提交
  10. 03 10月, 2013 1 次提交
  11. 31 8月, 2013 1 次提交
  12. 28 5月, 2013 1 次提交
  13. 19 3月, 2013 1 次提交
  14. 02 3月, 2013 1 次提交
  15. 15 1月, 2013 1 次提交
  16. 04 1月, 2013 1 次提交
  17. 20 12月, 2012 1 次提交
  18. 12 12月, 2012 1 次提交
  19. 08 12月, 2012 1 次提交
  20. 04 12月, 2012 1 次提交
  21. 20 11月, 2012 1 次提交
  22. 15 11月, 2012 1 次提交
    • K
      net/smsc911x: Fix ready check in cases where WORD_SWAP is needed · 769ce4c9
      Kamlakant Patel 提交于
      The chip ready check added by the commit 3ac3546e [Always wait for
      the chip to be ready] does not work when the register read/write
      is word swapped. This check has been added before the WORD_SWAP
      register is programmed, so we need to check for swapped register
      value as well.
      
      Bit 16 is marked as RESERVED in SMSC datasheet, Steve Glendinning
      <steve@shawell.net> checked with SMSC and wrote:
      
        The chip architects have concluded we should be reading PMT_CTRL
        until we see any of bits 0, 8, 16 or 24 set.  Then we should read
        BYTE_TEST to check the byte order is correct (as we already do).
      
        The rationale behind this is that some of the chip variants have
        word order swapping features too, so the READY bit could actually
        be in any of the 4 possible locations.  The architects have confirmed
        that if any of these 4 positions is set the chip is ready.  The other
        3 locations will either never be set or can only go high after READY
        does (so also indicate the device is ready).
      
      This change will check for the READY bit at the 16th position. We do
      not check the other two cases (bit 8 and 24) since the driver does not
      support byte-swapped register read/write.
      Signed-off-by: NKamlakant Patel <kamlakant.patel@broadcom.com>
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      769ce4c9
  23. 17 7月, 2012 1 次提交
  24. 23 6月, 2012 1 次提交
  25. 31 5月, 2012 1 次提交
  26. 22 4月, 2012 1 次提交
  27. 14 4月, 2012 1 次提交
  28. 04 4月, 2012 1 次提交
  29. 16 2月, 2012 1 次提交
  30. 01 2月, 2012 1 次提交
  31. 11 1月, 2012 1 次提交
  32. 04 1月, 2012 1 次提交
    • J
      net/smsc911x: Check if PHY is in operational mode before software reset · 6386994e
      Javier Martinez Canillas 提交于
      SMSC LAN generation 4 chips integrate an IEEE 802.3 ethernet physical layer.
      The PHY driver for this integrated chip enable an energy detect power-down mode.
      When the PHY is in a power-down mode, it prevents the MAC portion chip to be
      software reseted.
      
      That means that if we compile the kernel with the configuration option SMSC_PHY
      enabled and try to bring the network interface up without an cable plug-ed the
      PHY will be in a low power mode and the software reset will fail returning -EIO
      to user-space:
      
      root@igep00x0:~# ifconfig eth0 up
      ifconfig: SIOCSIFFLAGS: Input/output error
      
      This patch disable the energy detect power-down mode before trying to software
      reset the LAN chip and re-enables after it was reseted successfully.
      Signed-off-by: NJavier Martinez Canillas <javier@dowhile0.org>
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      6386994e
  33. 30 11月, 2011 1 次提交
    • R
      net/smsc911x: Add regulator support · c7e963f6
      Robert Marklund 提交于
      Add some basic regulator support for the power pins, as needed
      by the ST-Ericsson Snowball platform that powers up the SMSC911
      chip using an external regulator.
      
      Platforms that use regulators and the smsc911x and have no defined
      regulator for the smsc911x and claim complete regulator
      constraints with no dummy regulators will need to provide it, for
      example using a fixed voltage regulator. It appears that this may
      affect (apart from Ux500 Snowball) possibly these archs/machines
      that from some grep:s appear to define both CONFIG_SMSC911X and
      CONFIG_REGULATOR:
      
      - ARM Freescale mx3 and OMAP 2 plus, Raumfeld machines
      - Blackfin
      - Super-H
      
      Cc: Paul Mundt <lethal@linux-sh.org>
      Cc: linux-sh@vger.kernel.org
      Cc: Sascha Hauer <s.hauer@pengutronix.de>
      Cc: Tony Lindgren <tony@atomide.com>
      Cc: linux-omap@vger.kernel.org
      Cc: Mike Frysinger <vapier@gentoo.org>
      Cc: uclinux-dist-devel@blackfin.uclinux.org
      Reviewed-by: NMark Brown <broonie@opensource.wolfsonmicro.com>
      Signed-off-by: NRobert Marklund <robert.marklund@stericsson.com>
      Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      c7e963f6
  34. 14 11月, 2011 1 次提交
  35. 22 9月, 2011 1 次提交
  36. 18 8月, 2011 1 次提交
  37. 11 8月, 2011 1 次提交
    • J
      smsc: Move the SMC (SMSC) drivers · ae150435
      Jeff Kirsher 提交于
      Moves the SMC (SMSC) drivers into drivers/net/ethernet/smsc/ and the
      necessary Kconfig and Makefile changes.  Also did some cleanup
      of NET_VENDOR_SMC Kconfig tag for the 8390 based drivers.
      
      CC: Nicolas Pitre <nico@fluxnic.net>
      CC: Donald Becker <becker@scyld.com>
      CC: Erik Stahlman <erik@vt.edu>
      CC: Dustin McIntire <dustin@sensoria.com>
      CC: Steve Glendinning <steve.glendinning@smsc.com>
      CC: David Hinds <dahinds@users.sourceforge.net>
      Signed-off-by: NJeff Kirsher <jeffrey.t.kirsher@intel.com>
      ae150435