The board DTS are using numeric values instead of the defined GPIO
constanst to express polarity, use them to make the DTS more clear.
Signed-off-by: NJavier Martinez Canillas <javier@osg.samsung.com>
Signed-off-by: NKukjin Kim <kgene@kernel.org>

The board DTS are using numeric values instead of the defined GPIO
constanst to express polarity, use them to make the DTS more clear.
Signed-off-by: NJavier Martinez Canillas <javier@osg.samsung.com>
Signed-off-by: NKukjin Kim <kgene@kernel.org>

The Peach boards use the EC to store the vboot context information,
so add the corresponding properties on the EC node to indicate so.
Reviewed-by: NKrzysztof Kozlowski <k.kozlowski@samsung.com>
Acked-by: NJavier Martinez Canillas <javier@osg.samsung.com>
Signed-off-by: NEmilio Lopez <emilio.lopez@collabora.co.uk>
Signed-off-by: NKukjin Kim <kgene@kernel.org>

The regulator-compatible property from the regulator DT binding was
deprecated and the correct approach is to use the node's name.

This patch has no functional changes but by not using a deprecated
property, new DTS based on this one will not carry the same issue.
Signed-off-by: NJavier Martinez Canillas <javier@osg.samsung.com>
Signed-off-by: NKrzysztof Kozlowski <k.kozlowski@samsung.com>

This patch moves the display-timings node from fimd to dp to reflect the
device tree bindings change.
Signed-off-by: NSean Paul <seanpaul@chromium.org>
[tomeu.vizoso@collabora.com: Rebased]
Signed-off-by: NTomeu Vizoso <tomeu.vizoso@collabora.com>
Signed-off-by: NKrzysztof Kozlowski <k.kozlowski@samsung.com>

There are 2 revisions of the Exynos5250 Snow Chromebook that were
shipped: Rev4 and Rev5. The only difference between these 2 revisions
is the codec, Rev4 has a max98095 codec while Rev5 has a max98090.

Mainline only supports Rev4 so this patch moves the common device
nodes to a DTSI file and adds a DTS for the Exynos5250 Snow Rev5.

The Snow Rev5 DTS is based on the DTS found in the ChromiumOS 3.8
tree.
Signed-off-by: NJavier Martinez Canillas <javier@osg.samsung.com>
Tested-by: NMauro Carvalho Chehab <mchehab@osg.samsung.com>
Reviewed-by: NDouglas Anderson <dianders@chromium.org>
Signed-off-by: NKukjin Kim <kgene@kernel.org>

Use 'ldoN_reg: LDON' syntax and drop the deprecated
'regulator-compatible' property.
Signed-off-by: NTobias Jakobi <tjakobi@math.uni-bielefeld.de>
Reviewed-by: NJavier Martinez Canillas <javier@osg.samsung.com>
Signed-off-by: NKrzysztof Kozlowski <k.kozlowski@samsung.com>

The pinctrl settings in i2c_0 and i2c_1 are already provided
through the exynos4 dtsi.
Signed-off-by: NTobias Jakobi <tjakobi@math.uni-bielefeld.de>
Reviewed-by: NJavier Martinez Canillas <javier@osg.samsung.com>
Signed-off-by: NKrzysztof Kozlowski <k.kozlowski@samsung.com>

The change corrects cpu compatible property to a defined one,
see Documentation/devicetree/bindings/arm/cpus.txt
Signed-off-by: NVladimir Zapolskiy <vz@mleia.com>
Cc: Kukjin Kim <kgene@kernel.org>
Cc: Krzysztof Kozlowski <k.kozlowski@samsung.com>
Signed-off-by: NKrzysztof Kozlowski <k.kozlowski@samsung.com>

Add Hardkernel Odroid XU4 board Device Tree sources. The board differs
from Odroid XU3 and XU3-Lite by:
1. No green and red LEDs (except standard red power LED).
2. Only two PWM outputs are used (fan and blue LED)
3. No audio codec.
4. Two USB3 ports in host mode (no micro USB3 connector for OTG).
5. Realtek RTL8153-CG gigabit network adapter (instead of SMSC9514).
6. Additional connector with IO ports (I2S_0, I2C_5).
7. No DisplayPort (like XU3-Lite).
8. No TI INA231 power measurement sensors (like XU3-Lite).
Signed-off-by: NKrzysztof Kozlowski <k.kozlowski@samsung.com>
Reviewed-by: NJavier Martinez Canillas <javier@osg.samsung.com>
Signed-off-by: NKukjin Kim <kgene@kernel.org>

The Odroid XU4 board does not have audio codec so before adding DTS
for new board split the audio codec to separate DTSI file. Include
the audio codec DTSI in Odroid XU3 and XU3-Lite boards.
Signed-off-by: NKrzysztof Kozlowski <k.kozlowski@samsung.com>
Reviewed-by: NJavier Martinez Canillas <javier@osg.samsung.com>
Signed-off-by: NKukjin Kim <kgene@kernel.org>

The Odroid XU3 family boards have ACOKB pin of PMIC grounded, instead of
pulled up as usual. This means that PMIC must manually set PWRHOLD field
in its CTRL1 register to low before initiating power down.

This fixes Odroid XU3 powering off:
[   25.966053] reboot: Power down
[   25.967679] Power down.
[   26.070174] Power down failed, please power off system manually.
Signed-off-by: NKrzysztof Kozlowski <k.kozlowski.k@gmail.com>
Reported-by: NAnand Moon <linux.amoon@gmail.com>
Reviewed-by: NJavier Martinez Canillas <javier@osg.samsung.com>
Signed-off-by: NKukjin Kim <kgene@kernel.org>

With those bindings it is possible to use pwm-fan device available in
Odroid U3 as a cooling device.
Signed-off-by: NLukasz Majewski <l.majewski@samsung.com>
Acked-by: NEduardo Valentin <edubezval@gmail.com>
Reviewed-by: NKrzysztof Kozlowski <k.kozlowski@samsung.com>
Signed-off-by: NKukjin Kim <kgene@kernel.org>

Add pwm-fan node to the Odroid-U3 board file to enable PWM control of the
cooling fan. In addition, add the "pwm" label to the pwm@139D0000 node
in the exynos4412.dtsi.
Signed-off-by: NKamil Debski <k.debski@samsung.com>
Signed-off-by: NLukasz Majewski <l.majewski@samsung.com>
Reviewed-by: NKrzysztof Kozlowski <k.kozlowski@samsung.com>
Signed-off-by: NKukjin Kim <kgene@kernel.org>

Mark 800MHz OPP as a suspend opp for Exynos4412 based
boards so effectively cpufreq-dt driver behavior w.r.t.
suspend frequency matches what the old exynos-cpufreq
driver has been doing.

This patch fixes suspend/resume support on Exynos4412 based
Trats2 board and reboot hang on Exynos4412 based Odroid U3
board.

Cc: Thomas Abraham <thomas.ab@samsung.com>
Cc: Javier Martinez Canillas <javier@osg.samsung.com>
Cc: Marek Szyprowski <m.szyprowski@samsung.com>
Cc: Tobias Jakobi <tjakobi@math.uni-bielefeld.de>
Acked-by: NViresh Kumar <viresh.kumar@linaro.org>
Signed-off-by: NBartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>
Acked-by: NKrzysztof Kozlowski <k.kozlowski@samsung.com>
Signed-off-by: NKukjin Kim <kgene@kernel.org>

The LEDs on Odroid XU3 family boards could not properly probe
because PWM outputs were reduced only to PWM for fan. Fix it
for Odroid XU3 and XU3-Lite boards by switching to usage of
all 4 outputs (although the PWM for MIPI probably is redundant
because board does not have MIPI connector available).

This fixes warnings on dmesg:
[    4.838712] samsung-pwm 12dd0000.pwm: tried to request PWM channel 1 without output
[    4.838725] leds_pwm pwmleds: unable to request PWM for green:mmc0: -22
[    4.838767] leds_pwm: probe of pwmleds failed with error -22

Fixes: b685d540 ("ARM: dts: Add pwm-fan node for exynos5422-odroidxu3")
Signed-off-by: NKrzysztof Kozlowski <k.kozlowski.k@gmail.com>
Signed-off-by: NKukjin Kim <kgene@kernel.org>

Enable DMA transfers for serial ports.
Signed-off-by: NRobert Baldyga <r.baldyga@samsung.com>
Signed-off-by: NKrzysztof Kozlowski <k.kozlowski@samsung.com>

Use stdout-path so that we don't have to put the console on the
kernel command line.

Cc: Tim Bird <tim.bird@sonymobile.com>
Cc: Bjorn Andersson <bjorn.andersson@sonymobile.com>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

Use stdout-path so that we don't have to put the console on the
kernel command line.
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

Use stdout-path so that we don't have to put the console on the
kernel command line.
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

Use stdout-path so that we don't have to put the console on the
kernel command line.

Cc: Mathieu Olivari <mathieu@codeaurora.org>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

Use stdout-path so that we don't have to put the console on the
kernel command line.
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

Use stdout-path so that we don't have to put the console on the
kernel command line.
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

Use stdout-path so that we don't have to put the console on the
kernel command line.
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

Use stdout-path so that we don't have to put the console on the
kernel command line.
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

Use stdout-path so that we don't have to put the console on the
kernel command line.

Cc: Mike Rapoport <mike.rapoport@gmail.com>
Cc: Igor Grinberg <grinberg@compulab.co.il>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

Add a label to the serial nodes that are being used for the
console.
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

rtc can either be supplied from internal 32k clock or external crystal
generated 32k clock. Internal clock is SOC specific and the external
clock is board dependent. Adding the corresponding nodes.
Signed-off-by: NKeerthy <j-keerthy@ti.com>
Acked-by: NTony Lindgren <tony@atomide.com>
Signed-off-by: NAlexandre Belloni <alexandre.belloni@free-electrons.com>

Since the LED modes mapping is no longer hardcoded inside the leds-ns2
driver, then it must be provided through the modes-map property in the
ns2-leds nodes.
Signed-off-by: NVincent Donnefort <vdonnefort@gmail.com>
Acked-by: NGregory CLEMENT <gregory.clement@free-electrons.com>
Signed-off-by: NJacek Anaszewski <j.anaszewski@samsung.com>

The base addresses for the Ux500 PRCC controllers are hardcoded,
let's move them to the clock node in the device tree and delete
the constants.

Cc: Ulf Hansson <ulf.hansson@linaro.org>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
Acked-by: NOlof Johansson <olof@lixom.net>
Acked-by: NMichael Turquette <mturquette@baylibre.com>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

Specify how the GPIOs map to the pins in Tegra SoCs, so the dependency is
explicit.
Signed-off-by: NTomeu Vizoso <tomeu.vizoso@collabora.com>
Acked-by: NStephen Warren <swarren@nvidia.com>
Signed-off-by: NThierry Reding <treding@nvidia.com>

Current base address is wrong by 0x04 bytes for AHB bus device as shown
in dmesg:

	tegra-ahb 6000c004.ahb: incorrect AHB base address in DT data - enabling workaround

To correct old DTBs, commit ce7a10b0 ("ARM: 8334/1: amba: tegra-ahb:
detect and correct bogus base address") checks for the low bit of the
base address and removes theses 0x04 bytes at runtime.

This patch fixes the original DTS, so upstream version doesn't need the
workaround of the base address.

As both addresses are valid, this patch doesn't break compatibility.

Tested on tegra20-paz00 (aka ac100).
Signed-off-by: NNicolas Chauvet <kwizart@gmail.com>
Reviewed-by: NPaul Walmsley <paul@pwsan.com>
Signed-off-by: NThierry Reding <treding@nvidia.com>

This patch modifies the device tree for Tegra124 based devices to enable
the Cortex A15 PMU. The interrupt numbers are taken from NVIDIA Tegra K1
TRM (DP-06905-001_v03p). This patch was tested on a Jetson TK1.
Signed-off-by: NKyle Huey <khuey@kylehuey.com>
Acked-by: NMark Rutland <mark.rutland@arm.com>
Acked-by: NJon Hunter <jonathanh@nvidia.com>
Signed-off-by: NThierry Reding <treding@nvidia.com>

Add the device-tree node for the GK20A GPU and leave it disabled.
It is the responsibility of the bootloader to enable it if the
VPR registers have been programmed such that the GPU can operate.
Signed-off-by: NAlexandre Courbot <acourbot@nvidia.com>
Signed-off-by: NThierry Reding <treding@nvidia.com>

Add the device-tree node for the GK20A GPU and leave it disabled.
It is the responsibility of the bootloader to enable it if the
VPR registers have been programmed such that the GPU can operate.
Signed-off-by: NThierry Reding <treding@nvidia.com>
Signed-off-by: NAlexandre Courbot <acourbot@nvidia.com>

Nouveau can make use of the IOMMU to make physical appear linear in the
GPU address space.
Signed-off-by: NAlexandre Courbot <acourbot@nvidia.com>
Signed-off-by: NThierry Reding <treding@nvidia.com>

Specify the CPU voltage regulator for the cpufreq driver.
Signed-off-by: NTuomas Tynkkynen <ttynkkynen@nvidia.com>
Signed-off-by: NMikko Perttunen <mikko.perttunen@kapsi.fi>
Signed-off-by: NThierry Reding <treding@nvidia.com>

The Tegra124 cpufreq driver relies on certain clocks being present
in the /cpus/cpu@0 node.
Signed-off-by: NTuomas Tynkkynen <ttynkkynen@nvidia.com>
Signed-off-by: NMikko Perttunen <mikko.perttunen@kapsi.fi>
Signed-off-by: NThierry Reding <treding@nvidia.com>

Add the board-specific properties of the DFLL for the Jetson TK1 board.
On this board, the DFLL will take control of the sd0 regulator on the
on-board AS3722 PMIC.
Signed-off-by: NTuomas Tynkkynen <ttynkkynen@nvidia.com>
Signed-off-by: NMikko Perttunen <mikko.perttunen@kapsi.fi>
Acked-by: NMichael Turquette <mturquette@linaro.org>
Signed-off-by: NThierry Reding <treding@nvidia.com>

The DFLL clocksource is a separate IP block from the usual
clock-and-reset controller, so it gets its own device tree node.
Signed-off-by: NTuomas Tynkkynen <ttynkkynen@nvidia.com>
Signed-off-by: NMikko Perttunen <mikko.perttunen@kapsi.fi>
Acked-by: NMichael Turquette <mturquette@linaro.org>
Signed-off-by: NThierry Reding <treding@nvidia.com>