1. 29 10月, 2013 1 次提交
  2. 20 8月, 2013 1 次提交
    • W
      ARM: cacheflush: don't round address range up to nearest page · d9524dc3
      Will Deacon 提交于
      The flush_cache_user_range macro takes a pair of addresses describing
      the start and end of the virtual address range to flush. Due to an
      accidental oversight when flush_cache_range_user was introduced, the
      address range was rounded up so that the start and end addresses were
      page-aligned.
      
      For historical reference, the interesting commits in history.git are:
      
      10eacf1775e1 ("[ARM] Clean up ARM cache handling interfaces (part 1)")
      71432e79b76b ("[ARM] Add flush_cache_user_page() for sys_cacheflush()")
      
      This patch removes the alignment code, reducing the amount of flushing
      required for ranges that are not an exact multiple of PAGE_SIZE.
      Reviewed-by: NCatalin Marinas <catalin.marinas@arm.com>
      Reported-by: NJonathan Austin <jonathan.austin@arm.com>
      Signed-off-by: NWill Deacon <will.deacon@arm.com>
      d9524dc3
  3. 12 8月, 2013 1 次提交
  4. 17 6月, 2013 1 次提交
  5. 24 4月, 2013 1 次提交
  6. 25 9月, 2012 1 次提交
    • L
      ARM: mm: implement LoUIS API for cache maintenance ops · 031bd879
      Lorenzo Pieralisi 提交于
      ARM v7 architecture introduced the concept of cache levels and related
      control registers. New processors like A7 and A15 embed an L2 unified cache
      controller that becomes part of the cache level hierarchy. Some operations in
      the kernel like cpu_suspend and __cpu_disable do not require a flush of the
      entire cache hierarchy to DRAM but just the cache levels belonging to the
      Level of Unification Inner Shareable (LoUIS), which in most of ARM v7 systems
      correspond to L1.
      
      The current cache flushing API used in cpu_suspend and __cpu_disable,
      flush_cache_all(), ends up flushing the whole cache hierarchy since for
      v7 it cleans and invalidates all cache levels up to Level of Coherency
      (LoC) which cripples system performance when used in hot paths like hotplug
      and cpuidle.
      
      Therefore a new kernel cache maintenance API must be added to cope with
      latest ARM system requirements.
      
      This patch adds flush_cache_louis() to the ARM kernel cache maintenance API.
      
      This function cleans and invalidates all data cache levels up to the
      Level of Unification Inner Shareable (LoUIS) and invalidates the instruction
      cache for processors that support it (> v7).
      
      This patch also creates an alias of the cache LoUIS function to flush_kern_all
      for all processor versions prior to v7, so that the current cache flushing
      behaviour is unchanged for those processors.
      
      v7 cache maintenance code implements a cache LoUIS function that cleans and
      invalidates the D-cache up to LoUIS and invalidates the I-cache, according
      to the new API.
      Reviewed-by: NSantosh Shilimkar <santosh.shilimkar@ti.com>
      Reviewed-by: NNicolas Pitre <nico@linaro.org>
      Signed-off-by: NLorenzo Pieralisi <lorenzo.pieralisi@arm.com>
      Tested-by: NShawn Guo <shawn.guo@linaro.org>
      031bd879
  7. 31 7月, 2012 1 次提交
  8. 02 5月, 2012 1 次提交
  9. 20 4月, 2012 1 次提交
  10. 12 2月, 2011 1 次提交
  11. 03 2月, 2011 2 次提交
  12. 05 10月, 2010 1 次提交
  13. 19 9月, 2010 2 次提交
  14. 08 5月, 2010 1 次提交
  15. 26 3月, 2010 1 次提交
  16. 20 2月, 2010 1 次提交
  17. 15 2月, 2010 2 次提交
  18. 06 2月, 2010 1 次提交
  19. 20 1月, 2010 1 次提交
  20. 14 12月, 2009 3 次提交
  21. 04 12月, 2009 1 次提交
  22. 02 12月, 2009 1 次提交
  23. 26 11月, 2009 1 次提交
    • I
      block: add helpers to run flush_dcache_page() against a bio and a request's pages · 2d4dc890
      Ilya Loginov 提交于
      Mtdblock driver doesn't call flush_dcache_page for pages in request.  So,
      this causes problems on architectures where the icache doesn't fill from
      the dcache or with dcache aliases.  The patch fixes this.
      
      The ARCH_IMPLEMENTS_FLUSH_DCACHE_PAGE symbol was introduced to avoid
      pointless empty cache-thrashing loops on architectures for which
      flush_dcache_page() is a no-op.  Every architecture was provided with this
      flush pages on architectires where ARCH_IMPLEMENTS_FLUSH_DCACHE_PAGE is
      equal 1 or do nothing otherwise.
      
      See "fix mtd_blkdevs problem with caches on some architectures" discussion
      on LKML for more information.
      Signed-off-by: NIlya Loginov <isloginov@gmail.com>
      Cc: Ingo Molnar <mingo@elte.hu>
      Cc: David Woodhouse <dwmw2@infradead.org>
      Cc: Peter Horton <phorton@bitbox.co.uk>
      Cc: "Ed L. Cashin" <ecashin@coraid.com>
      Signed-off-by: NJens Axboe <jens.axboe@oracle.com>
      2d4dc890
  24. 30 10月, 2009 1 次提交
    • R
      ARM: Fix errata 411920 workarounds · df71dfd4
      Russell King 提交于
      Errata 411920 indicates that any "invalidate entire instruction cache"
      operation can fail if the right conditions are present.  This is not
      limited just to those operations in flush.c, but elsewhere.  Place the
      workaround in the already existing __flush_icache_all() function
      instead.
      Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
      df71dfd4
  25. 24 9月, 2009 1 次提交
  26. 14 6月, 2009 1 次提交
  27. 25 3月, 2009 1 次提交
  28. 23 3月, 2009 1 次提交
    • E
      [ARM] pxa: add base support for Marvell's PXA168 processor line · 49cbe786
      Eric Miao 提交于
      """The Marvell® PXA168 processor is the first in a family of application
      processors targeted at mass market opportunities in computing and consumer
      devices. It balances high computing and multimedia performance with low
      power consumption to support extended battery life, and includes a wealth
      of integrated peripherals to reduce overall BOM cost .... """
      
      See http://www.marvell.com/featured/pxa168.jsp for more information.
      
        1. Marvell Mohawk core is a hybrid of xscale3 and its own ARM core,
           there are many enhancements like instructions for flushing the
           whole D-cache, and so on
      
        2. Clock reuses Russell's common clkdev, and added the basic support
           for UART1/2.
      
        3. Devices are a bit different from the 'mach-pxa' way, the platform
           devices are now dynamically allocated only when necessary (i.e.
           when pxa_register_device() is called). Description for each device
           are stored in an array of 'struct pxa_device_desc'. Now that:
      
           a. this array of device description is marked with __initdata and
              can be freed up system is fully up
      
           b. which means board code has to add all needed devices early in
              his initializing function
      
           c. platform specific data can now be marked as __initdata since
              they are allocated and copied by platform_device_add_data()
      
        4. only the basic UART1/2/3 are added, more devices will come later.
      Signed-off-by: NJason Chagas <chagas@marvell.com>
      Signed-off-by: NEric Miao <eric.miao@marvell.com>
      49cbe786
  29. 30 11月, 2008 1 次提交
  30. 06 11月, 2008 1 次提交
  31. 01 9月, 2008 1 次提交
  32. 03 8月, 2008 1 次提交
  33. 27 7月, 2008 2 次提交
  34. 03 7月, 2008 1 次提交