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  1. 17 8月, 2015 5 次提交
    • M
      xtensa: implement fake NMI · 38fef73c
      由 Max Filippov 提交于 
      In case perf IRQ is the highest of the medium-level IRQs, and is alone
on its level, it may be treated as NMI:
- LOCKLEVEL is defined to be one level less than EXCM level,
- IRQ masking never lowers current IRQ level,
- new fake exception cause code, EXCCAUSE_MAPPED_NMI is assigned to that
  IRQ; new second level exception handler, do_nmi, assigned to it
  handles it as NMI,
- atomic operations in configurations without s32c1i still need to mask
  all interrupts.

Cc: Peter Zijlstra <a.p.zijlstra@chello.nl>
Acked-by: NPeter Zijlstra (Intel) <peterz@infradead.org>
Signed-off-by: NMax Filippov <jcmvbkbc@gmail.com>
      38fef73c
    • M
      xtensa: don't touch EXC_TABLE_FIXUP in _switch_to · 98e29832
      由 Max Filippov 提交于 
      There's no way _switch_to can produce double exceptions now, don't
enter/leave EXC_TABLE_FIXUP critical section.
Signed-off-by: NMax Filippov <jcmvbkbc@gmail.com>
      98e29832
    • M
      xtensa: fix kernel register spilling · 77d6273e
      由 Max Filippov 提交于 
      call12 can't be safely used as the first call in the inline function,
because the compiler does not extend the stack frame of the bounding
function accordingly, which may result in corruption of local variables.

If a call needs to be done, do call8 first followed by call12.

For pure assembly code in _switch_to increase stack frame size of the
bounding function.

Cc: stable@vger.kernel.org
Signed-off-by: NMax Filippov <jcmvbkbc@gmail.com>
      77d6273e
    • M
      xtensa: reorganize irq flags tracing · 7d5f6a9a
      由 Max Filippov 提交于 
      entry.s only disables IRQs on hardware IRQ, move trace_hardirqs_off call
into do_interrupt. Check actual intlevel that will be restored on return
from exception handler to decide if trace_hardirqs_on should be called.
Annotate IRQ on/off points in the TIF_* handling loop on return from
exception handler.
Signed-off-by: NMax Filippov <jcmvbkbc@gmail.com>
      7d5f6a9a
    • M
      xtensa: keep exception/interrupt stack continuous · b6569439
      由 Max Filippov 提交于 
      Restore original a0 in the kernel exception stack frame. This way it
looks like the frame that got interrupt/exception did alloca (copy a0 and
a1 spilled under old stack to the new location as well) to save registers
and then did a call to handler.
The point where interrupt/exception was taken is not in the stack chain,
only in pt_regs (call4 from that address can be simulated to keep it in
the stack trace).
Signed-off-by: NMax Filippov <jcmvbkbc@gmail.com>
      b6569439
  3. 15 7月, 2015 1 次提交
  5. 14 8月, 2014 4 次提交
    • M
      xtensa: deprecate fast_xtensa and fast_spill_registers syscalls · 9184289c
      由 Max Filippov 提交于 
      These syscalls are not used by userspace tools for some time now, and
they have issues when called with invalid arguments. It's not worth
changing signal delivery mechanism as we don't expect any new users for
these syscalls. Let's keep them for backwards compatibility under #ifdef,
disabled by default.
Signed-off-by: NMax Filippov <jcmvbkbc@gmail.com>
      9184289c
    • M
      xtensa: fix a6 and a7 handling in fast_syscall_xtensa · d1b6ba82
      由 Max Filippov 提交于 
      Remove restoring a6 on some return paths and instead modify and restore
it in a single place, using symbolic name.
Correctly restore a7 from PT_AREG7 in case of illegal a6 value.

Cc: stable@vger.kernel.org
Signed-off-by: NMax Filippov <jcmvbkbc@gmail.com>
      d1b6ba82
    • M
      xtensa: fix TLBTEMP_BASE_2 region handling in fast_second_level_miss · 7128039f
      由 Max Filippov 提交于 
      Current definition of TLBTEMP_BASE_2 is always 32K above the
TLBTEMP_BASE_1, whereas fast_second_level_miss handler for the TLBTEMP
region analyzes virtual address bit (PAGE_SHIFT + DCACHE_ALIAS_ORDER)
to determine TLBTEMP region where the fault happened. The size of the
TLBTEMP region is also checked incorrectly: not 64K, but twice data
cache way size (whicht may as well be less than the instruction cache
way size).

Fix TLBTEMP_BASE_2 to be TLBTEMP_BASE_1 + data cache way size.
Provide TLBTEMP_SIZE that is a greater of doubled data cache way size or
the instruction cache way size, and use it to determine if the second
level TLB miss occured in the TLBTEMP region.

Practical occurence of page faults in the TLBTEMP area is extremely
rare, this code can be tested by deletion of all w[di]tlb instructions
in the tlbtemp_mapping region.

Cc: stable@vger.kernel.org
Signed-off-by: NMax Filippov <jcmvbkbc@gmail.com>
      7128039f
    • M
      xtensa: fix access to THREAD_RA/THREAD_SP/THREAD_DS · 52247123
      由 Max Filippov 提交于 
      With SMP and a lot of debug options enabled task_struct::thread gets out
of reach of s32i/l32i instructions with base pointing at task_struct,
breaking build with the following messages:

  arch/xtensa/kernel/entry.S: Assembler messages:
  arch/xtensa/kernel/entry.S:1002: Error: operand 3 of 'l32i.n' has invalid value '1048'
  arch/xtensa/kernel/entry.S:1831: Error: operand 3 of 's32i.n' has invalid value '1040'
  arch/xtensa/kernel/entry.S:1832: Error: operand 3 of 's32i.n' has invalid value '1044'

Change base to point to task_struct::thread in such cases.
Don't use a10 in _switch_to to save/restore prev pointer as a2 is not
clobbered.

Cc: stable@vger.kernel.org
Signed-off-by: NMax Filippov <jcmvbkbc@gmail.com>
      52247123
  7. 29 1月, 2014 1 次提交
    • C
      xtensa: fix fast_syscall_spill_registers · 6b5a1f74
      由 Chris Zankel 提交于 
      The original implementation could clobber registers under certain conditions.

The Xtensa processor architecture uses windowed registers and the original
implementation was using a4 as a temporary register, which under certain
conditions could be register a0 of the oldest window frame, and didn't always
restore the content correctly.

By moving the _spill_registers routine inside the fast system call, it frees
up one more register (the return address is not required anymore) for the
spill routine.
Signed-off-by: NChris Zankel <chris@zankel.net>
      6b5a1f74
  9. 26 1月, 2014 2 次提交
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