1. 15 6月, 2017 9 次提交
    • L
      drm/i915: add KBL GT2/GT3 check macros · 3891589e
      Lionel Landwerlin 提交于
      Add macros to detect GT2/GT3 skus so we can apply the proper OA
      configuration later.
      Signed-off-by: NLionel Landwerlin <lionel.g.landwerlin@intel.com>
      Reviewed-by: NMatthew Auld <matthew.auld@intel.com>
      Signed-off-by: NBen Widawsky <ben@bwidawsk.net>
      3891589e
    • R
      drm/i915/perf: remove perf.hook_lock · 1bef3409
      Robert Bragg 提交于
      In earlier iterations of the i915-perf driver we had a number of
      callbacks/hooks from other parts of the i915 driver to e.g. notify us
      when a legacy context was pinned and these could run asynchronously with
      respect to the stream file operations and might also run in atomic
      context.
      
      dev_priv->perf.hook_lock had been for serialising access to state needed
      within these callbacks, but as the code has evolved some of the hooks
      have gone away or are implemented to avoid needing to lock any state.
      
      The remaining use of this lock was actually redundant considering how
      the gen7 oacontrol state used to be updated as part of a context pin
      hook.
      Signed-off-by: NRobert Bragg <robert@sixbynine.org>
      Signed-off-by: NLionel Landwerlin <lionel.g.landwerlin@intel.com>
      Reviewed-by: NMatthew Auld <matthew.auld@intel.com>
      Signed-off-by: NBen Widawsky <ben@bwidawsk.net>
      1bef3409
    • R
      drm/i915/perf: per-gen timebase for checking sample freq · 155e941f
      Robert Bragg 提交于
      An oa_exponent_to_ns() utility and per-gen timebase constants where
      recently removed when updating the tail pointer race condition WA, and
      this restores those so we can update the _PROP_OA_EXPONENT validation
      done in read_properties_unlocked() to not assume we have a 12.5MHz
      timebase as we did for Haswell.
      
      Accordingly the oa_sample_rate_hard_limit value that's referenced by
      proc_dointvec_minmax defining the absolute limit for the OA sampling
      frequency is now initialized to (timestamp_frequency / 2) instead of the
      6.25MHz constant for Haswell.
      
      v2:
          Specify frequency of 19.2MHz for BXT (Ville)
          Initialize oa_sample_rate_hard_limit per-gen too (Lionel)
      Signed-off-by: NRobert Bragg <robert@sixbynine.org>
      Signed-off-by: NLionel Landwerlin <lionel.g.landwerlin@intel.com>
      Reviewed-by: NMatthew Auld <matthew.auld@intel.com>
      Signed-off-by: NBen Widawsky <ben@bwidawsk.net>
      155e941f
    • R
      drm/i915/perf: Add more OA configs for BDW, CHV, SKL + BXT · fc599211
      Robert Bragg 提交于
      These are auto generated from an XML description of metric sets,
      currently maintained in gputop, ref:
      
       https://github.com/rib/gputop
       > gputop-data/oa-*.xml
       > scripts/i915-perf-kernelgen.py
      
       $ make -C gputop-data -f Makefile.xml
      Signed-off-by: NRobert Bragg <robert@sixbynine.org>
      Signed-off-by: NLionel Landwerlin <lionel.g.landwerlin@intel.com>
      Reviewed-by: NMatthew Auld <matthew.auld@intel.com>
      Signed-off-by: NBen Widawsky <ben@bwidawsk.net>
      fc599211
    • R
      drm/i915/perf: Add OA unit support for Gen 8+ · 19f81df2
      Robert Bragg 提交于
      Enables access to OA unit metrics for BDW, CHV, SKL and BXT which all
      share (more-or-less) the same OA unit design.
      
      Of particular note in comparison to Haswell: some OA unit HW config
      state has become per-context state and as a consequence it is somewhat
      more complicated to manage synchronous state changes from the cpu while
      there's no guarantee of what context (if any) is currently actively
      running on the gpu.
      
      The periodic sampling frequency which can be particularly useful for
      system-wide analysis (as opposed to command stream synchronised
      MI_REPORT_PERF_COUNT commands) is perhaps the most surprising state to
      have become per-context save and restored (while the OABUFFER
      destination is still a shared, system-wide resource).
      
      This support for gen8+ takes care to consider a number of timing
      challenges involved in synchronously updating per-context state
      primarily by programming all config state from the cpu and updating all
      current and saved contexts synchronously while the OA unit is still
      disabled.
      
      The driver intentionally avoids depending on command streamer
      programming to update OA state considering the lack of synchronization
      between the automatic loading of OACTXCONTROL state (that includes the
      periodic sampling state and enable state) on context restore and the
      parsing of any general purpose BB the driver can control. I.e. this
      implementation is careful to avoid the possibility of a context restore
      temporarily enabling any out-of-date periodic sampling state. In
      addition to the risk of transiently-out-of-date state being loaded
      automatically; there are also internal HW latencies involved in the
      loading of MUX configurations which would be difficult to account for
      from the command streamer (and we only want to enable the unit when once
      the MUX configuration is complete).
      
      Since the Gen8+ OA unit design no longer supports clock gating the unit
      off for a single given context (which effectively stopped any progress
      of counters while any other context was running) and instead supports
      tagging OA reports with a context ID for filtering on the CPU, it means
      we can no longer hide the system-wide progress of counters from a
      non-privileged application only interested in metrics for its own
      context. Although we could theoretically try and subtract the progress
      of other contexts before forwarding reports via read() we aren't in a
      position to filter reports captured via MI_REPORT_PERF_COUNT commands.
      As a result, for Gen8+, we always require the
      dev.i915.perf_stream_paranoid to be unset for any access to OA metrics
      if not root.
      
      v5: Drain submitted requests when enabling metric set to ensure no
          lite-restore erases the context image we just updated (Lionel)
      
      v6: In addition to drain, switch to kernel context & update all
          context in place (Chris)
      
      v7: Add missing mutex_unlock() if switching to kernel context fails
          (Matthew)
      
      v8: Simplify OA period/flex-eu-counters programming by using the
          batchbuffer instead of modifying ctx-image (Lionel)
      
      v9: Back to updating the context image (due to erroneous testing,
          batchbuffer programming the OA unit doesn't actually work)
          (Lionel)
          Pin context before updating context image (Chris)
          Drop MMIO programming now that we switch to a kernel context with
          right values in initial context image (Chris)
      
      v10: Just pin_map the contexts we want to modify or let the
           configuration happen on first use (Chris)
      
      v11: Update kernel context OA config through the batchbuffer rather
           than on the fly ctx-image update (Lionel)
      
      v12: Rework OA context registers update again by swithing away from
           user contexts and reconfiguring the kernel context through the
           batchbuffer and updating all the other contexts' context image.
           Also take care to lock slice/subslice configuration when OA is
           on. (Lionel)
      
      v13: Request rpcs updates on all engine when updating the OA config
           (Lionel)
      
      v14: Drop any kind of rpcs management now that we monitor sseu
           configuration changes in a later patch (Lionel)
           Remove usleep after programming the NOA configs on Gen8+, this
           doesn't seem to be needed (Lionel)
      
      v15: Respect coding style for block comments (Chris)
      
      v16: Add missing i915_add_request() in case we fail to emit OA
           configuration (Matthew)
      Signed-off-by: NRobert Bragg <robert@sixbynine.org>
      Signed-off-by: NLionel Landwerlin <lionel.g.landwerlin@intel.com>
      Reviewed-by: Matthew Auld <matthew.auld@intel.com> \o/
      Signed-off-by: NBen Widawsky <ben@bwidawsk.net>
      19f81df2
    • R
      drm/i915/perf: Add 'render basic' Gen8+ OA unit configs · 5182f646
      Robert Bragg 提交于
      Adds a static OA unit, MUX, B Counter + Flex EU configurations for basic
      render metrics on Broadwell, Cherryview, Skylake and Broxton. These are
      auto generated from an XML description of metric sets, currently
      maintained in gputop, ref:
      
       https://github.com/rib/gputop
       > gputop-data/oa-*.xml
       > scripts/i915-perf-kernelgen.py
      
       $ make -C gputop-data -f Makefile.xml WHITELIST=RenderBasic
      
      v2: add newlines to debug messages + fix comment (Matthew Auld)
      Signed-off-by: NRobert Bragg <robert@sixbynine.org>
      Signed-off-by: NLionel Landwerlin <lionel.g.landwerlin@intel.com>
      Reviewed-by: NMatthew Auld <matthew.auld@intel.com>
      Signed-off-by: NBen Widawsky <ben@bwidawsk.net>
      5182f646
    • L
      drm/i915/perf: rework mux configurations queries · 3f488d99
      Lionel Landwerlin 提交于
      Gen8+ might have mux configurations per slices/subslices. Depending on
      whether slices/subslices have been fused off, only part of the
      configuration needs to be applied. This change reworks the mux
      configurations query mechanism to allow more than one set of registers
      to be programmed.
      
      v2: s/n_mux_regs/n_mux_configs/ (Matthew)
      Signed-off-by: NLionel Landwerlin <lionel.g.landwerlin@intel.com>
      Reviewed-by: NMatthew Auld <matthew.auld@intel.com>
      Signed-off-by: NBen Widawsky <ben@bwidawsk.net>
      3f488d99
    • R
      drm/i915: expose _SUBSLICE_MASK GETPARM · f5320233
      Robert Bragg 提交于
      Assuming a uniform mask across all slices, this enables userspace to
      determine the specific sub slices can be enabled. This information is
      required, for example, to be able to analyse some OA counter reports
      where the counter configuration depends on the HW sub slice
      configuration.
      Signed-off-by: NRobert Bragg <robert@sixbynine.org>
      Reviewed-by: NMatthew Auld <matthew.auld@intel.com>
      Signed-off-by: NLionel Landwerlin <lionel.g.landwerlin@intel.com>
      Signed-off-by: NBen Widawsky <ben@bwidawsk.net>
      f5320233
    • R
      drm/i915: expose _SLICE_MASK GETPARM · 7fed555c
      Robert Bragg 提交于
      Enables userspace to determine the maximum number of slices that can
      be enabled on the device and also know what specific slices can be
      enabled. This information is required, for example, to be able to
      analyse some OA counter reports where the counter configuration
      depends on the HW slice configuration.
      Signed-off-by: NRobert Bragg <robert@sixbynine.org>
      Reviewed-by: NMatthew Auld <matthew.auld@intel.com>
      Signed-off-by: NLionel Landwerlin <lionel.g.landwerlin@intel.com>
      Signed-off-by: NBen Widawsky <ben@bwidawsk.net>
      7fed555c
  2. 14 6月, 2017 5 次提交
  3. 13 6月, 2017 19 次提交
  4. 12 6月, 2017 4 次提交
  5. 10 6月, 2017 3 次提交