at91sam9g45, at91sam9x5 and sama5 SoCs should not use
"atmel,at91sam9rl-udc" for their USB device compatible property since
this compatible is attached to a specific hardware bug fix.
Signed-off-by: NBoris Brezillon <boris.brezillon@free-electrons.com>
Acked-by: NAlexandre Belloni <alexandre.belloni@free-electrons.com>
Tested-by: NBo Shen <voice.shen@atmel.com>
Acked-by: NNicolas Ferre <nicolas.ferre@atmel.com>
Cc: <stable@vger.kernel.org>  #4.0+
Signed-off-by: NKevin Hilman <khilman@linaro.org>

Add standby domain gpio controller for APM X-Gene SoC platform.
Signed-off-by: NY Vo <yvo@apm.com>
Acked-by: NLinus Walleij <linus.walleij@linaro.org>
Signed-off-by: NKevin Hilman <khilman@linaro.org>

This backs out all changes that were added in the hip04-dt
branch after various boot problems were discovered in UEFI booting.
Reported-by: NTyler Baker <tyler.baker@linaro.org>
Cc: Wei Xu <xuwei5@hisilicon.com>
[khilman: minor changelog updates]
Signed-off-by: NArnd Bergmann <arnd@arndb.de>
Signed-off-by: NKevin Hilman <khilman@linaro.org>

v3.18 changed handle_IRQ() to call __handle_domain_irq(), which now
rejects attempts to deliver IRQ0.  Since IRQ 0 is used as the timer
interrupt (just like the PIT on x86), this causes boot to fail as the
bogomips calibration never completes.

Fix this by shuffling all interrupts up by one.

Fixes: a71b092a ("ARM: Convert handle_IRQ to use __handle_domain_irq")
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
Signed-off-by: NGregory CLEMENT <gregory.clement@free-electrons.com>

The current Armada XP suspend to RAM implementation, as added in
commit 27432825 ("ARM: mvebu: Armada XP GP specific
suspend/resume code") does not handle big-endian configurations
properly: the small bit of assembly code putting the DRAM in
self-refresh and toggling the GPIOs to turn off power forgets to
convert the values to little-endian.

This commit fixes that by making sure the two values we will write to
the DRAM controller register and GPIO register are already in
little-endian before entering the critical assembly code.
Signed-off-by: NThomas Petazzoni <thomas.petazzoni@free-electrons.com>
Cc: <stable@vger.kernel.org> # v3.19+
Fixes: 27432825 ("ARM: mvebu: Armada XP GP specific suspend/resume code")

Following the merge of "pinctrl: mvebu: armada-xp: rename spi to spi0"
by Linus Walleij, we need to adjust the Armada XP Device Tree
accordingly, by adjusting the pinctrl configuration for SPI pins.
Signed-off-by: NThomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: NGregory CLEMENT <gregory.clement@free-electrons.com>
Signed-off-by: NGregory CLEMENT <gregory.clement@free-electrons.com>

lapic.timer_mode was not properly initialized after migration, which
broke few useful things, like login, by making every sleep eternal.

Fix this by calling apic_update_lvtt in kvm_apic_post_state_restore.

There are other slowpaths that update lvtt, so this patch makes sure
something similar doesn't happen again by calling apic_update_lvtt
after every modification.

Cc: stable@vger.kernel.org
Fixes: f30ebc31 ("KVM: x86: optimize some accesses to LVTT and SPIV")
Signed-off-by: NRadim Krčmář <rkrcmar@redhat.com>
Signed-off-by: NMarcelo Tosatti <mtosatti@redhat.com>

commit dcf9a03b (ARM: multi_v7_defconfig: Enable PMIC and MUIC
drivers for exynos) mistakenly added an duplicate line for
CONFIG_COMMON_CLK_QCOM=y.  Remove it.
Signed-off-by: NKevin Hilman <khilman@linaro.org>

Fix:
arch/arm/kernel/sleep.S:121: Error: selected processor does not support ARM opcodes
arch/arm/kernel/sleep.S:123: Error: attempt to use an ARM instruction on a Thumb-only processor -- `adr r9,1f+1'
arch/arm/kernel/sleep.S:124: Error: attempt to use an ARM instruction on a Thumb-only processor -- `bx r9'
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>

Some platforms always enter the kernel in the ARM state even if
the kernel is compiled for THUMB2. Add a small wrapper on top of
cpu_resume() that switches into THUMB2 state.

This provides the functionality to fix a problem reported by Kevin
Hilman on next-20150601 where the ifc6410 fails to boot a THUMB2
kernel because the platform's firmware always enters the kernel in
ARM mode from deep idle states.

(rmk: tweaked to work without BSYM->badr changes.)
Reported-by: NKevin Hilman <khilman@linaro.org>
Cc: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Cc: Lina Iyer <lina.iyer@linaro.org>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>

Add basic defconfig support to zx SOC, including uart, mmc
 and other common config
Signed-off-by: NJun Nie <jun.nie@linaro.org>
Signed-off-by: NKevin Hilman <khilman@linaro.org>

Add initial dts file and document for ZX296702 and board ZX296702-AD1.
More peripherals will be added later.
Signed-off-by: NJun Nie <jun.nie@linaro.org>
Signed-off-by: NKevin Hilman <khilman@linaro.org>

After commit 02b4e275 (ARM: v7 setup function should invalidate L1
cache) the soc specific secondary_startup is removed, causing build
failures:

../arch/arm/mach-socfpga/platsmp.c: In function 'socfpga_a10_boot_secondary':
../arch/arm/mach-socfpga/platsmp.c:66:140: error: 'socfpga_secondary_startup' undeclared (first use in this function)
../arch/arm/mach-socfpga/platsmp.c:66:140: note: each undeclared identifier is reported only once for each function it appears in

To fix, use the generic secondary_startup.

Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
Signed-off-by: NKevin Hilman <khilman@linaro.org>

Enable the Exynos DSI and S6E8AA0 panel for full X11 display on Trats2.
Signed-off-by: NKrzysztof Kozlowski <k.kozlowski@samsung.com>
Signed-off-by: NKukjin Kim <kgene@kernel.org>
Signed-off-by: NKevin Hilman <khilman@linaro.org>

This includes setting up EGPIOs 0 and 9 for card detection and
chip select respectively. This patch is needed to mount a root
filesystem on the SPI-based MMC card reader found on the Sim.One.
Signed-off-by: NMika Westerberg <mika.westerberg@iki.fi>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
Reviewed-by: NH Hartley Sweeten <hsweeten@visionengravers.com>
Signed-off-by: NKevin Hilman <khilman@linaro.org>

Adjust device tree entry to the proper registered compatible
string for LIS3LV02DL.
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
Signed-off-by: NKevin Hilman <khilman@linaro.org>

The Juno board, and likely many other boards, likes to use simple
GPIO keys for input events. Enabled this in the default
ARM64 defconfig.
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
Reviewed-by: NShannon Zhao <shannon.zhao@linaro.org>
Signed-off-by: NKevin Hilman <khilman@linaro.org>

The Juno board has two keys connected to a PL061 GPIO block,
in accordance to DDI0524B "ARM Versatile Express Juno Development
Platform" revision 1.0, table 2-4 "GPIO (0) and GPIO (1) used
for additional user key entry". By trial-and-error I found that
these are connected to the two keys named "power" and "home"
on the motherboard.

Register the GPIO block and these two keys in the device tree
using the PL061 GPIO driver and the generic gpio keys.

- Map POWER, HOME, VOL+ and VOL- to the obvious input events.
- Map RLOCK to KEY_SCREENLOCK/KEY_COFFEE unless someone can
  explain better what this is for.
- Map the NMI button to KEY_SYSREQ as this is used like so
  in the SYSREQ debugging hack.
Acked-by: NLiviu Dudau <Liviu.Dudau@arm.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
Signed-off-by: NKevin Hilman <khilman@linaro.org>

The xdmac channel configuration is done in one cell not two. This error
prevents from probing devices correctly.
Signed-off-by: NLudovic Desroches <ludovic.desroches@atmel.com>
Fixes: 83906783 ("ARM: at91/dt: sama5d4: add aes, sha and tdes nodes")
Cc: stable@vger.kernel.org # 4.1
Acked-by: NNicolas Ferre <nicolas.ferre@atmel.com>
Signed-off-by: NKevin Hilman <khilman@linaro.org>

Fix this compile issue with gcc-4.4.4:

   arch/x86/kvm/mmu.c: In function 'kvm_mmu_pte_write':
   arch/x86/kvm/mmu.c:4256: error: unknown field 'cr0_wp' specified in initializer
   arch/x86/kvm/mmu.c:4257: error: unknown field 'cr4_pae' specified in initializer
   arch/x86/kvm/mmu.c:4257: warning: excess elements in union initializer
   ...

gcc-4.4.4 (at least) has issues when using anonymous unions in
initializers.

Fixes: edc90b7d ("KVM: MMU: fix SMAP virtualization")
Cc: Xiao Guangrong <guangrong.xiao@linux.intel.com>
Cc: Paolo Bonzini <pbonzini@redhat.com>
Cc: Davidlohr Bueso <dave@stgolabs.net>
Signed-off-by: NAndrew Morton <akpm@linux-foundation.org>
Signed-off-by: NLinus Torvalds <torvalds@linux-foundation.org>

Enable netcp driver in defconfig for keystone SoCs.
Signed-off-by: NMurali Karicheri <m-karicheri2@ti.com>
Signed-off-by: NSantosh Shilimkar <ssantosh@kernel.org>
Signed-off-by: NKevin Hilman <khilman@linaro.org>

Add code that requests that the sdr controller go into
self-refresh mode.  This code is run from ocram.

Suspend-to-RAM and EDAC support are mutually exclusive on
SOCFPGA.  If the EDAC is enabled, it will prevent the
platform from going into suspend.

Example of how to request to suspend to ram:
 $ echo enabled > \
/sys/devices/soc/ffc02000.serial0/tty/ttyS0/power/wakeup

 $ echo -n mem > /sys/power/state
Signed-off-by: NAlan Tull <atull@opensource.altera.com>
Signed-off-by: NDinh Nguyen <dinguyen@opensource.altera.com>
Signed-off-by: NKevin Hilman <khilman@linaro.org>

The STMicrolectornics's STM32F429 MCU has the following main features:
 - Cortex-M4 core running up to @180MHz
 - 2MB internal flash, 256KBytes internal RAM
 - FMC controller to connect SDRAM, NOR and NAND memories
 - SD/MMC/SDIO support
 - Ethernet controller
 - USB OTFG FS & HS controllers
 - I2C, SPI, CAN busses support
 - Several 16 & 32 bits general purpose timers
 - Serial Audio interface
 - LCD controller
Tested-by: NChanwoo Choi <cw00.choi@samsung.com>
Signed-off-by: NMaxime Coquelin <mcoquelin.stm32@gmail.com>
Signed-off-by: NKevin Hilman <khilman@linaro.org>

Update the arria10 gmac nodes with all the necessary properties for ethernet
to function on the Arria10 devkit.
Signed-off-by: NDinh Nguyen <dinguyen@opensource.altera.com>
Signed-off-by: NKevin Hilman <khilman@linaro.org>

k2l netcp range size is 16M (0x1000000) and not 0xffffff. This patch fixes
this. Similarly fix the size of switch module register space to 0x20000.
Signed-off-by: NMurali Karicheri <m-karicheri2@ti.com>
Signed-off-by: NSantosh Shilimkar <ssantosh@kernel.org>

k2e netcp range size is 16M (0x1000000) and not 0xffffff. This patch fixes
this. Similarly fix the size of switch module register space to 0x20000.
Signed-off-by: NMurali Karicheri <m-karicheri2@ti.com>
Signed-off-by: NSantosh Shilimkar <ssantosh@kernel.org>

k2hk netcp range size is 1M (0x100000) and not 0xfffff. This patch fixes
this.
Signed-off-by: NMurali Karicheri <m-karicheri2@ti.com>
Signed-off-by: NSantosh Shilimkar <ssantosh@kernel.org>

This patch enables networking on k2l evm by providing
device bindings for netcp, knav, and qmss. See device
binding documentation at

Documentation/devicetree/bindings/net/keystone-netcp.txt
Signed-off-by: NWingMan Kwok <w-kwok2@ti.com>
Signed-off-by: NMurali Karicheri <m-karicheri2@ti.com>
Signed-off-by: NSantosh Shilimkar <ssantosh@kernel.org>

This patch enables networking on k2e evm by adding device
bindings for netcp, knav and qmss. See device binding
documentation below for details.

Documentation/devicetree/bindings/net/keystone-netcp.txt
Signed-off-by: NWingMan Kwok <w-kwok2@ti.com>
Signed-off-by: NMurali Karicheri <m-karicheri2@ti.com>
Signed-off-by: NSantosh Shilimkar <ssantosh@kernel.org>

This patch enables networking on k2hk evm by adding device
bindings for netcp, knav and qmss.  See device binding
documentation below for details.

Documentation/devicetree/bindings/net/keystone-netcp.txt
Signed-off-by: NWingMan Kwok <w-kwok2@ti.com>
Signed-off-by: NMurali Karicheri <m-karicheri2@ti.com>
Signed-off-by: NSantosh Shilimkar <ssantosh@kernel.org>

Add boot_secondary implementation for the Arria10 platform. Bringing up
the secondary core on the Arria 10 platform is pretty similar to the
Cyclone/Arria 5 platform, with the exception of the following differences:

- Register offset to bringup CPU1 out of reset is different.
- The cpu1-start-addr for Arria10 contains an additional nibble.
Signed-off-by: NDinh Nguyen <dinguyen@opensource.altera.com>
Signed-off-by: NKevin Hilman <khilman@linaro.org>

Convert cyclone5/arria5 to use CPU_METHOD_OF_DECLARE for smp operations.
Signed-off-by: NDinh Nguyen <dinguyen@opensource.altera.com>
Signed-off-by: NKevin Hilman <khilman@linaro.org>

The latest version of modinfo fails to compile score architecture
targets with the following error.

FATAL: The relocation at __ex_table+0x634 references
section "__ex_table" which is not executable, IOW
the kernel will fault if it ever tries to
jump to it.  Something is seriously wrong
and should be fixed.

The probem is caused by a bad label in an __ex_table entry.
Acked-by: NLennox Wu <lennox.wu@gmail.com>
Cc: Quentin Casasnovas <quentin.casasnovas@oracle.com>
Signed-off-by: NGuenter Roeck <linux@roeck-us.net>

Fix

include/asm-generic/io.h: In function 'readb':
include/asm-generic/io.h:113:2: error:
	implicit declaration of function 'bfin_read8'
include/asm-generic/io.h: In function 'readw':
include/asm-generic/io.h:121:2: error:
	implicit declaration of function 'bfin_read16'
include/asm-generic/io.h: In function 'readl':
include/asm-generic/io.h:129:2: error:
	implicit declaration of function 'bfin_read32'
include/asm-generic/io.h: In function 'writeb':
include/asm-generic/io.h:147:2: error:
	implicit declaration of function 'bfin_write8'
include/asm-generic/io.h: In function 'writew':
include/asm-generic/io.h:155:2: error:
	implicit declaration of function 'bfin_write16'
include/asm-generic/io.h: In function 'writel':
include/asm-generic/io.h:163:2: error:
	implicit declaration of function 'bfin_write32'
Reported-by: NGeert Uytterhoeven <geert@linux-m68k.org>
Fixes: 1a3372bc ("blackfin: io: define __raw_readx/writex with
	bfin_readx/writex")
Cc: Steven Miao <realmz6@gmail.com>
Signed-off-by: NGuenter Roeck <linux@roeck-us.net>

Due to the slightly odd way that new threads and processes start execution
when scheduled for the very first time they were bypassing the required
disable_msa call.
Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

If CONFIG_SERIAL_8250 is set to m, the Loongson seria.ko module might get
unloaded while the serial driver modules are still loaded resulting in
stale references to the destroyed platform_device instance.

Anyway, platform devices should always be registered indicated what
devices are present, _not_ what drivers have been configured.
Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
Reported-by: NPaul Gortmaker <paul.gortmaker@windriver.com>
Patchwork: https://patchwork.linux-mips.org/patch/10538/

If CONFIG_MTD_PHYSMAP is set to m, the Cobalt mtd.ko module might get
unloaded while the drivers/mtd modules are still loaded resulting in
stale references to the destroyed platform_device instance.

Anyway, platform devices should always be registered indicated what
devices are present, _not_ what drivers have been configured.
Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

This reverts commit c05199e5.

Vince Weaver reported the following crash while perf fuzzing:

[   79.473121] kernel BUG at mm/vmalloc.c:1335!
[   79.694391] Call Trace:
[   79.696997]  <IRQ>
[   79.699090]  [<ffffffff811b2130>] get_vm_area_caller+0x40/0x50
[   79.705505]  [<ffffffff81039f4d>] ? snb_uncore_imc_init_box+0x6d/0x90
[   79.712414]  [<ffffffff810635e5>] __ioremap_caller+0x195/0x350
[   79.718610]  [<ffffffff81039f4d>] ? snb_uncore_imc_init_box+0x6d/0x90
[   79.725462]  [<ffffffff81427f6b>] ? debug_object_activate+0x14b/0x1e0
[   79.732346]  [<ffffffff810637b7>] ioremap_nocache+0x17/0x20
[   79.738283]  [<ffffffff81039f4d>] snb_uncore_imc_init_box+0x6d/0x90
[   79.744945]  [<ffffffff81039cf7>] snb_uncore_imc_event_start+0xb7/0x110
[   79.752020]  [<ffffffff81039d97>] snb_uncore_imc_event_add+0x47/0x60
[   79.758832]  [<ffffffff81162cbb>] event_sched_in.isra.85+0xfb/0x330
[   79.765519]  [<ffffffff81162f5f>] group_sched_in+0x6f/0x1e0
[   79.771481]  [<ffffffff8101df1a>] ? native_sched_clock+0x2a/0x90
[   79.777858]  [<ffffffff811637bc>] __perf_event_enable+0x25c/0x2a0
[   79.784418]  [<ffffffff810f3e69>] ? tick_nohz_irq_exit+0x29/0x30
[   79.790820]  [<ffffffff8115ef30>] ? cpu_clock_event_start+0x40/0x40
[   79.797546]  [<ffffffff8115ef80>] remote_function+0x50/0x60
[   79.803535]  [<ffffffff810f8cd1>] flush_smp_call_function_queue+0x81/0x180
[   79.810840]  [<ffffffff810f9763>] generic_smp_call_function_single_interrupt+0x13/0x60
[   79.819328]  [<ffffffff8104b5e8>] smp_trace_call_function_single_interrupt+0x38/0xc0
[   79.827614]  [<ffffffff816de9be>] trace_call_function_single_interrupt+0x6e/0x80
[   79.835465]  <EOI>
[   79.837543]  [<ffffffff8156e8b5>] ? cpuidle_enter_state+0x65/0x160
[   79.844377]  [<ffffffff8156e8a1>] ? cpuidle_enter_state+0x51/0x160
[   79.851015]  [<ffffffff8156e9e7>] cpuidle_enter+0x17/0x20
[   79.856791]  [<ffffffff810b6e39>] cpu_startup_entry+0x399/0x440
[   79.863165]  [<ffffffff816c9ddb>] rest_init+0xbb/0xd0

The offending commit is clearly confused as it moves heavy initialization
work into IPI context.

Revert it.
Reported-by: NVince Weaver <vincent.weaver@maine.edu>
Acked-by: NPeter Zijlstra (Intel) <peterz@infradead.org>
Cc: Kan Liang <kan.liang@intel.com>
Cc: Arnaldo Carvalho de Melo <acme@kernel.org>
Cc: Stephane Eranian <eranian@google.com>
Cc: Yan, Zheng <zheng.z.yan@intel.com>
Cc: linux-kernel@vger.kernel.org
Signed-off-by: NIngo Molnar <mingo@kernel.org>

Commit be0c37c9 ("MIPS: Rearrange PTE bits into fixed positions.")
rearranged the PTE bits into fixed positions in preparation for the XPA
support. However, this patch broke R6 since it only took R2 cores
into consideration for the RI/XI bits leading to boot failures. We fix
this by adding the missing CONFIG_CPU_MIPSR6 definitions

Fixes: be0c37c9 ("MIPS: Rearrange PTE bits into fixed positions.")
Cc: Steven J. Hill <Steven.Hill@imgtec.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/10208/Signed-off-by: NMarkos Chandras <markos.chandras@imgtec.com>
Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

CBOX counters are increased to 48b on HSX.

Correct the MSR address for HSWEP_U_MSR_PMON_CTR0 and
HSWEP_U_MSR_PMON_CTL0.

See specification in:
http://www.intel.com/content/www/us/en/processors/xeon/
xeon-e5-v3-uncore-performance-monitoring.html
Signed-off-by: NKan Liang <kan.liang@intel.com>
Signed-off-by: NPeter Zijlstra (Intel) <peterz@infradead.org>
Cc: Andrew Morton <akpm@linux-foundation.org>
Cc: H. Peter Anvin <hpa@zytor.com>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Thomas Gleixner <tglx@linutronix.de>
Link: http://lkml.kernel.org/r/1432645835-7918-1-git-send-email-kan.liang@intel.comSigned-off-by: NIngo Molnar <mingo@kernel.org>