On Renesas ARM SoCs (SH/R-Mobile, R-Car, RZ), the CPG (Clock Pulse
Generator) and MSSR (Module Standby and Software Reset) blocks are
intimately connected, and share the same register block.

Hence it makes sense to describe these two blocks using a
single device node in DT, instead of using a hierarchical structure with
multiple nodes, using a mix of generic and SoC-specific bindings.

These new DT bindings are intended to replace the existing DT bindings
for CPG core clocks ("renesas,*-cpg-clocks", "renesas,cpg-div6-clock")
and module clocks ("renesas,*-mstp-clocks"), at least for new SoCs.

This will make it easier to add module reset support later, which is
currently not implemented, and difficult to achieve using the existing
bindings due to the intertwined register layout.
Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be>
Acked-by: NMichael Turquette <mturquette@baylibre.com>
Reviewed-by: NMagnus Damm <damm+renesas@opensource.se>

ST's Low Power Controller can currently operate in two supported modes;
Watchdog and Real Time Clock.  These defines will aid engineers to easily
identify the selected mode.
Signed-off-by: NLee Jones <lee.jones@linaro.org>
Reviewed-by: NGuenter Roeck <linux@roeck-us.net>
Signed-off-by: NWim Van Sebroeck <wim@iguana.be>

Signed-off-by: NCharles Keepax <ckeepax@opensource.wolfsonmicro.com>
Signed-off-by: NLee Jones <lee.jones@linaro.org>

Add a binding document for the USB2.0 PHY found on the IMG Pistachio SoC.
Signed-off-by: NAndrew Bresticker <abrestic@chromium.org>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: Pawel Moll <pawel.moll@arm.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Ian Campbell <ijc+devicetree@hellion.org.uk>
Cc: Kumar Gala <galak@codeaurora.org>
Cc: Kishon Vijay Abraham I <kishon@ti.com>
Cc: devicetree@vger.kernel.org
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Cc: James Hartley <james.hartley@imgtec.com>
Cc: Damien Horsley <Damien.Horsley@imgtec.com>
Patchwork: https://patchwork.linux-mips.org/patch/9727/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

Document the devicetree binding for Ingenic SoC CGUs, and add headers
defining the clock specifiers for clocks provided by the JZ4740 & JZ4780
CGU blocks.
Signed-off-by: NPaul Burton <paul.burton@imgtec.com>
Cc: Ian Campbell <ijc+devicetree@hellion.org.uk>
Cc: Kumar Gala <galak@codeaurora.org>
Cc: Lars-Peter Clausen <lars@metafoo.de>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Mike Turquette <mturquette@linaro.org>
Cc: Pawel Moll <pawel.moll@arm.com>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: devicetree@vger.kernel.org
Cc: linux-mips@linux-mips.org
Cc: devicetree@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/10152/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

Add driver for NXP LPC18xx/43xx Clock Control Unit (CCU). The CCU
provides fine grained gating of most clocks present in the SoC.
Signed-off-by: NJoachim Eastwood <manabian@gmail.com>
Signed-off-by: NMichael Turquette <mturquette@baylibre.com>

Add driver for NXP LPC18xx/43xx Clock Generation Unit (CGU). The CGU
contains several clock generators and output stages that route the
clocks either directly to peripherals or to a Clock Control Unit
(CCU).
Signed-off-by: NJoachim Eastwood <manabian@gmail.com>
Signed-off-by: NMichael Turquette <mturquette@baylibre.com>

The Broadcom Cygnus SoC is architected under the iProc architecture. It
has the following PLLs: ARMPLL, GENPLL, LCPLL0, MIPIPLL, all dervied
from an onboard crystal. Cygnus also has various ASIU clocks that are
derived directly from the onboard crystal.
Signed-off-by: NRay Jui <rjui@broadcom.com>
Reviewed-by: NScott Branden <sbranden@broadcom.com>
Signed-off-by: NMichael Turquette <mturquette@baylibre.com>

Add clocks defines for the global clock controller
found on ZTE ZX296702 SoCs.
Signed-off-by: NJun Nie <jun.nie@linaro.org>
Acked-by: NStephen Boyd <sboyd@codeaurora.org>
Signed-off-by: NKevin Hilman <khilman@linaro.org>

This patchset adds the infrastructure for registering and managing the
core clocks found on Amlogic MesonX SoCs. In particular:

- PLLs
- CPU clock
- Fixed rate clocks, fixed factor clocks, ...
Signed-off-by: NCarlo Caione <carlo@endlessm.com>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

Binding header file for clock input selection and configuration.
Signed-off-by: NPeter Ujfalusi <peter.ujfalusi@ti.com>
Signed-off-by: NMark Brown <broonie@kernel.org>

Timer has external fast clock, and it is a mux clock.
Add the timer clock type for timer driver.
Signed-off-by: NChao Xie <chao.xie@marvell.com>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

USB will drive clock from USB_PLL.
Signed-off-by: NChao Xie <chao.xie@marvell.com>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

Add support for the TI dp83867 Gigabit ethernet phy
device.

The DP83867 is a robust, low power, fully featured
Physical Layer transceiver with integrated PMD
sublayers to support 10BASE-T, 100BASE-TX and
1000BASE-T Ethernet protocols.
Signed-off-by: NDan Murphy <dmurphy@ti.com>
Signed-off-by: NDavid S. Miller <davem@davemloft.net>

Add the header file "hi6220-clock.h" used by both
hi6220 clock driver and hi6220 device tree file.
Suggested-by: NStephen Boyd <sboyd@codeaurora.org>
Signed-off-by: NBintian Wang <bintian.wang@huawei.com>
Tested-by: NWill Deacon <will.deacon@arm.com>
Tested-by: NTyler Baker <tyler.baker@linaro.org>
Tested-by: NKevin Hilman <khilman@linaro.org>
Signed-off-by: NMichael Turquette <mturquette@linaro.org>

Enabled DAP (debug access port) by default. This enables the hw-
breakpoint framework to make use of the breakpoints and watchpoints
supported by hardware.

[    0.215805] hw-breakpoint: found 2 (+1 reserved) breakpoint and 1 watchpoint registers.
[    0.224624] hw-breakpoint: maximum watchpoint size is 4 bytes.

Without this clock, the hw-breakpoint driver claims an undefined
instruction during initialization:
[    0.227380] hw-breakpoint: Debug register access (0xee003e17) caused undefined instruction on CPU 0
[    0.227519] hw-breakpoint: CPU 0 failed to disable vector catch
Signed-off-by: NStefan Agner <stefan@agner.ch>
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>

It adds the imx7d clock ID definitions which will be used by both imx7d
clock driver and device tree.
Signed-off-by: NFrank Li <Frank.Li@freescale.com>
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>

Add the NSS/GMAC clocks and the TCM clock and NSS resets.
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>
Signed-off-by: NMathieu Olivari <mathieu@codeaurora.org>
Signed-off-by: NDavid S. Miller <davem@davemloft.net>

This patch adds apq8016 lpass driver support. APQ8016 has 4 MI2S which
can be routed to one internal codec and 2 external codec interfaces.

Primary, Secondary, Quaternary I2S can do Rx(playback) and Tertiary and
Quaternary can do Tx(capture).
Tested-by: NKenneth Westfield <kwestfie@codeaurora.org>
Acked-by: NKenneth Westfield <kwestfie@codeaurora.org>
Signed-off-by: NSrinivas Kandagatla <srinivas.kandagatla@linaro.org>
Signed-off-by: NMark Brown <broonie@kernel.org>

Adding the jack type to the dt-bindings directory will allow for device
tree files to specify the type of audio jacks that are present for a
board.
Signed-off-by: NDylan Reid <dgreid@chromium.org>
Signed-off-by: NMark Brown <broonie@kernel.org>

enable mmc3 used for wlan and uart3 used for bluetooth

configure the gpios used for wlan and bluetooth controls

add fixed voltage regulator used for wlan power control
Signed-off-by: NEyal Reizer <eyalr@ti.com>
Signed-off-by: NTony Lindgren <tony@atomide.com>

Add pinfunc header file, mt8135/mt8173 relate dts will include it.
Signed-off-by: NHongzhou Yang <hongzhou.yang@mediatek.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

This patch add support for select accessory detect mode to HPDETL or HPDETR.
Arizona provides a headphone detection circuit on the HPDETL and HPDETR pins
to measure the impedance of an external load connected to the headphone.

Depending on board design, headphone detect pins can change to HPDETR or HPDETL.
Signed-off-by: NInha Song <ideal.song@samsung.com>
Acked-by: NLee Jones <lee@kernel.org>
Acked-by: NCharles Keepax <ckeepax@opensource.wolfsonmicro.com>
Signed-off-by: NChanwoo Choi <cw00.choi@samsung.com>

This creates include/dt-bindings/clock/samsung,s2mps11.h with
the three 32kHz clock outputs from the s2mps11 mfd.
Signed-off-by: NMarkus Reichl <m.reichl@fivetechno.de>
Signed-off-by: NKrzysztof Kozlowski <k.kozlowski.k@gmail.com>
Signed-off-by: NKukjin Kim <kgene@kernel.org>

This adds the clock binding documentation for the Marvell PXA1928 SOC.
The PXA1928 has 3 clock control blocks for different subsystems of the
chip.
Signed-off-by: NRob Herring <robh@kernel.org>
Cc: Pawel Moll <pawel.moll@arm.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Ian Campbell <ijc+devicetree@hellion.org.uk>
Cc: Kumar Gala <galak@codeaurora.org>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

This new header file defines pincontrol constants to use
from bcm2835 DTS files for pincontrol properties option.
Reviewed-by: NStephen Warren <swarren@wwwdotorg.org>
Signed-off-by: NStefan Wahren <stefan.wahren@i2se.com>
Signed-off-by: NLee Jones <lee.jones@linaro.org>

Link the external IRQ controller irqc0 to the IRQC module clock, so it
can be power managed using that clock.
Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>

Link the external IRQ controller irqc0 to the IRQC module clock, so it
can be power managed using that clock.
Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>

Link the external IRQ controller irqc0 to the IRQC module clock, so it
can be power managed using that clock.
Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>

Link the external IRQ controllers irqc0 and irqc1 to the IRQC module
clock, so they can be power managed using that clock.
Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be>
[horms: corrected typo in changelog to refer to r8a73a4]
Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>

This patch adds basic clocks for MT8173, including TOPCKGEN, PLLs,
INFRA and PERI clocks.
Signed-off-by: NJames Liao <jamesjj.liao@mediatek.com>
Signed-off-by: NHenry Chen <henryc.chen@mediatek.com>
Signed-off-by: NSascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

This patch adds basic clocks for MT8135, including TOPCKGEN, PLLs,
INFRA and PERI clocks.
Signed-off-by: NJames Liao <jamesjj.liao@mediatek.com>
Signed-off-by: NHenry Chen <henryc.chen@mediatek.com>
Signed-off-by: NSascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

ST's Low Power Controller can currently operate in two supported modes;
Watchdog and Real Time Clock.  These defines will aid engineers to easily
identify the selected mode.
Reviewed-by: NGuenter Roeck <linux@roeck-us.net>
Acked-by: NMaxime Coquelin <maxime.coquelin@st.com>
Signed-off-by: NLee Jones <lee.jones@linaro.org>

The current parent, plld_out0, does not exist. The proper name is
pll_d_out0. While at it, rename the plld_dsi clock to pll_d_dsi_out to
be more consistent with other clock names.

Fixes: b270491e ("clk: tegra: Define PLLD_DSI and remove dsia(b)_mux")
Signed-off-by: NThierry Reding <treding@nvidia.com>

Add compatible string definitions and supported pin functions.
Signed-off-by: NIvan T. Ivanov <ivan.ivanov@linaro.org>
Acked-by: NBjorn Andersson <bjorn.andersson@sonymobile.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

This patch adds support for the AmLogic Meson8b SoC.
Signed-off-by: NCarlo Caione <carlo@endlessm.com>
Acked-by: NBeniamino Galvani <b.galvani@gmail.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

The NAND controller within EBI2 requires EBI2_CLK and
EBI2_ALWAYS_ON_CLK clocks.  Create structs for these clocks so
that they can be used by the NAND controller driver. Add an entry
for EBI2_AON_CLK in the gcc-ipq806x DT binding document.
Signed-off-by: NArchit Taneja <architt@codeaurora.org>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

Add clocks/resets defines for the global clock controller
found on Qualcomm MSM8916 SoCs.
Signed-off-by: NGeorgi Djakov <georgi.djakov@linaro.org>
Signed-off-by: NKumar Gala <galak@codeaurora.org>
Signed-off-by: NOlof Johansson <olof@lixom.net>

Now there are generic phy type constants declared in phy.h, migrate over to
using them rather than defining our own. This change has been done as one
atomic commit to be bisectable.

Note: The values of the defines are the same, so there is no ABI breakage
with this patch.
Signed-off-by: NPeter Griffin <peter.griffin@linaro.org>
Acked-by: NRob Herring <robh@kernel.org>
Acked-by: NLee Jones <lee.jones@linaro.org>
Acked-by: NMaxime Coquelin <maxime.coquelin@st.com>
Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com>

Xilinx platforms have no hardwired video capture or video processing
interface. Users create capture and memory to memory processing
pipelines in the FPGA fabric to suit their particular needs, by
instantiating video IP cores from a large library.

The Xilinx Video IP core is a framework that models a video pipeline
described in the device tree and expose the pipeline to userspace
through the media controller and V4L2 APIs.
Signed-off-by: NLaurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: NHyun Kwon <hyun.kwon@xilinx.com>
Signed-off-by: NRadhey Shyam Pandey <radheys@xilinx.com>
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>
Acked-by: NHans Verkuil <hans.verkuil@cisco.com>
Signed-off-by: NMauro Carvalho Chehab <mchehab@osg.samsung.com>