Clean up the init code and move the creation of factor clocks to the
appropriate positions coming from the clock architecture diagrams.

This also unifies the artificial separation of the hclk_vcodec etc clocks
again.

We do keep the separate definition of some watchdog and usb480m pseudo
clocks for now, as they're not real factor clocks from the clock-tree
but placeholders for fixes to come (usb480m gets supplied by the
missing driver for the new usbphy type and the watchdog-gate is sitting
somewhere else together which we cannot model currently).
Signed-off-by: NHeiko Stuebner <heiko@sntech.de>

I2S_2CH set freq need to select parent and calculate parent freq.
so just mark it as the CLK_SET_RATE_PARENT flag.
Signed-off-by: Nzhangqing <zhangqing@rock-chips.com>
Signed-off-by: NHeiko Stuebner <heiko@sntech.de>

SPDIF_8CH set freq need to select parent and calculate parent freq.
so just mark it as the CLK_SET_RATE_PARENT flag.
Signed-off-by: Nzhangqing <zhangqing@rock-chips.com>
Signed-off-by: NHeiko Stuebner <heiko@sntech.de>

The edp_24m parent select bit define is:
1'b0:xin24m
1'b1:1'b0(dummy)
so adapt the parent sel bit to the currect one.
Signed-off-by: Nzhangqing <zhangqing@rock-chips.com>
Signed-off-by: NHeiko Stuebner <heiko@sntech.de>

Fix a typo making the sclk_hdmi_cec access a wrong register to handle
its gate.

Fixes: 3536c97a ("clk: rockchip: add rk3368 clock controller")
Signed-off-by: NHeiko Stuebner <heiko@sntech.de>
Reviewed-by: Nzhangqing <zhangqing@rock-chips.com>
Cc: stable@vger.kernel.org

The vdpu and vepu clocks can also be parented to the npll and current
parent list also is wrong as it would use the npll as "usbphy" source,
so adapt the parent to the correct one.

Fixes: 3536c97a ("clk: rockchip: add rk3368 clock controller")
Signed-off-by: NHeiko Stuebner <heiko@sntech.de>
Reviewed-by: Nzhangqing <zhangqing@rock-chips.com>
Cc: stable@vger.kernel.org

Similar to commit 9880d427 ("clk: rockchip: fix rk3288 cpuclk core
dividers") it seems the cpuclk dividers are one to high on the rk3368
as well.

And again similar to the previous fix, we opt to make the divider list
contain the values to be written to use the same paradigm for them on all
supported socs.

Fixes: 3536c97a ("clk: rockchip: add rk3368 clock controller")
Reported-by: NZhang Qing <zhangqing@rock-chips.com>
Signed-off-by: NHeiko Stuebner <heiko@sntech.de>
Reviewed-by: Nzhangqing <zhangqing@rock-chips.com>
Cc: stable@vger.kernel.org

Both clusters have their mux bit in bit 7 of their respective register.
For whatever reason the big cluster currently lists bit 15 which is
definitly wrong.

Fixes: 3536c97a ("clk: rockchip: add rk3368 clock controller")
Reported-by: NZhang Qing <zhangqing@rock-chips.com>
Signed-off-by: NHeiko Stuebner <heiko@sntech.de>
Reviewed-by: Nzhangqing <zhangqing@rock-chips.com>
Cc: stable@vger.kernel.org

As commit 1d33929e ("clk: rockchip: switch PLLs to slow mode before
reboot for rk3288") states, switching the PLLs to slow-mode is only
necessary when rebooting using the soft-reset done through the CRU.

The dwc2 controllers used create really big number of interrupts in
special constellations involving usb-hubs and their number is so high,
it can even overwhelm the interrupt handler if the cpu-speed os to low.

Right now the PLLs are put into slow-mode in a shutdown syscore_ops
callback which means it happens on all reboots (not only the soft-reset
ones) and even on poweroff actions.

This can result in the system not powering off and getting stuck instead,
so we should move the slow-mode change nearer to the actual reboot action.

For this we introduce the possiblity to also set a callback that gets
called from the restart-handler directly prior to restarting the system
and move the shutdown-callback to this new option.

With this the slow-mode switch is done only on the necessary reboots
and also has a smaller possibility of causing artifacts.

Fixes: 1d33929e ("clk: rockchip: switch PLLs to slow mode before reboot for rk3288")
Signed-off-by: NHeiko Stuebner <heiko.stuebner@collabora.com>
Reviewed-by: NDouglas Anderson <dianders@chromium.org>

Due to a copy-paste error the the rk3368 cpuclk settings were acessing
rk3288-specific register offsets. This never caused problems till now,
as cpu frequency scaling in't used currently at all.
Reported-by: NXing Zheng <zhengxing@rock-chips.com>
Signed-off-by: NHeiko Stuebner <heiko@sntech.de>

Add aclk_bus and aclk_peri to the list of rk3368 critical clocks,
which are the base clocks that supply for all peripherals, never
to be disabled automatically.
Signed-off-by: NJianqun xu <jay.xu@rock-chips.com>
Signed-off-by: NHeiko Stuebner <heiko@sntech.de>

Most rk3368 boards (especially those with Pmic that followed the lead
from rk3368-evb-act8846) have a PWM regulator on them for vdd_logic.
This is the main voltage for all kinds of misc stuff including the
memory controller.

On these boards it is critically important to make sure that the PWM
never ever glitches and never loses its clock. Any glitch could
crash the system.

Right now there are no users of the PWM regulator and also Linux
thinks that the PWM regulator is disabled.  Things happen to work
because firmware configured the PWM and Linux doesn't touch it.
..and the PWM's clock is marked as "ignore unused".

...but things _stop_ working if we turn off serial console.  Why?
Because:
    1. Serial console shares a parent clock with the PWM (pclk_cpu)
    2. If we have no serial console then nobody is holding pclk_cpu on
       at reboot time.  It gets disabled.

We need to fix a lot of the above problems, but until we get
everything right the cleanest "hack" seems like it is to just keep
the "rk_pwm" clock on always.
Signed-off-by: NCaesar Wang <wxt@rock-chips.com>
Signed-off-by: NHeiko Stuebner <heiko@sntech.de>

Again a result of the gpio-clock-liberation the rk3368 needs the
pclk_pd_pmu marked as critical, to boot successfully.
Reported-by: NMark Rutland <mark.rutland@arm.com>
Signed-off-by: NHeiko Stuebner <heiko@sntech.de>
Tested-by: NMark Rutland <mark.rutland@arm.com>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

Describe the clock tree and software resets of the rk3368 ARM64 SoC
Signed-off-by: NHeiko Stuebner <heiko@sntech.de>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>